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Core Debug
10.2.3
Debug Core Register Data Register
10.2.4
Debug Exception and Monitor Control Register
10-8
The purpose of the Debug Core Register Data Register (DCRDR) is to hold data for
reading and writing registers to and from the processor.
The DCRDR:
•
is a 32-bit read/write register
•
address
0xE000EDF8.
This is the data value written to the register selected by the Debug Register Selector
Register.
When the processor receives a request from the Debug Core Register Selector, this
register is read or written by the processor using a normal load-store unit operation.
If core register transfers are not being performed, this register can be used by
software-based debug monitors for communication in non-halting debug. For example,
OS RSD and Real View Monitor. This enables flags and bits to be used to acknowledge
state and indicate if commands have been accepted to, replied to, or accepted and
replied to.
The purpose of the Debug Exception and Monitor Control Register (DEMCR) is for:
•
Vector catching. That is, to cause debug entry when a specified vector is
committed for execution.
•
Debug monitor control.
The DEMCR:
•
is a 32-bit read/write register
•
address
0xE000EDFC
Figure 10-2 on page 10-6 shows the arrangement of bits in the register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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