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Debug Port
12-30
Note
When overrun detection is enabled a WAIT response must include a data phase. See
Sticky overrun behavior on page 12-30 for more information.
Normally, when a debugger receives a WAIT response it retries the same operation. This
enables it to process data as quickly as possible. However, if several retries have been
attempted, and time allowed for a slow interconnection and memory system to respond,
if appropriate, the debugger might write to the ABORT register. This signals to the
active AP that it must terminate the transfer that it is currently attempting. An AP
implementation might be unable to terminate a transfer on its ASIC interface. However,
on receiving an ABORT request the AP must free up the Serial Wire Debug interface.
Writing to the ABORT register after receiving a WAIT response means the debugger
can then access other parts of the debug system.
The FAULT response
SW-DP does not issue a FAULT response to an access to the IDCODE, CTRL/STAT or
ABORT registers. For any other access, the SW-DP issues a FAULT response if any
sticky flag is set in the CTRL/STAT Register, see The Control/Status Register,
CTRL/STAT on page 12-53. See Sticky overrun behavior for more information about the
sticky overrun flag.
Use of the FAULT response enables the protocol to remain synchronized. A debugger
might stream a block of data and then check the CTRL/STAT register at the end of the
block.
The sticky error flags are cleared by writing bits in the ABORT register, see The Abort
Register, ABORT on page 12-49.
Sticky overrun behavior
If SW-DP receives a transaction request when the previous transaction has not
completed it generates a WAIT response. If overrun detection is enabled in the
CTRL/STAT Register, the STICKYORUN flag is set to 1 in that register. For more
information see The Control/Status Register, CTRL/STAT on page 12-53. Subsequent
transactions generate FAULT responses, because a sticky flag is set.
When overrun detection is enabled, WAIT and FAULT responses require a data phase:
•
if the transaction is a read the data in the data phase is Unpredictable
•
if the transaction is a write the data phase is ignored.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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