ARM Cortex-M3 Technical Reference Manual page 65

Name of register
.
Irq 224 to 239 Clear Enable Register
Irq 0 to 31 Set Pending Register
.
.
.
Irq 224 to 239 Set Pending Register
Irq 0 to 31 Clear Pending Register
.
.
.
Irq 224 to 239 Clear Pending Register
Irq 0 to 31 Active Bit Register
.
.
.
Irq 224 to 239 Active Bit Register
Irq 0 to 31 Priority Register
.
.
.
Irq 236 to 239 Priority Register
CPUID Base Register
Interrupt Control State Register
ARM DDI 0337B Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 3-1 NVIC registers (continued)
Type Address
. .
0xE000E19C
Read/write
0xE000E200
Read/write
. .
. .
. .
0xE000E21C
Read/write
0xE000E280
Read/write
. .
. .
. .
Read/write 0xE000E29C
Read-only 0xE000E300
. .
. .
. .
0xE000E31C
Read-only
0xE000E400
Read/write
. .
. .
. .
0xE000E4F0
Read/write
0xE000ED00
Read-only
0xE000ED04
Read/write
or read-only
System Control
Reset value
.
0x00000000
0x00000000
.
.
.
0x00000000
0x00000000
.
.
.
0x00000000
0x00000000
.
.
.
0x00000000
0x00000000
.
.
.
0x00000000
0x410FC230
0x00000000
3-3