Table of Contents
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Introduction
Operation
Move immediate 16-bit value to bottom halfword [15:0] of
register and clear top halfword [31:16]
Move to register from status
Move to status register
Multiply two signed or unsigned register values
No operation
Logical OR NOT register value with immediate 12-bit value
Logical OR NOT register value with shifted register value
Logical OR register value with immediate 12-bit value
Logical OR register value with shifted register value
Reverse bit order
Reverse bytes in word
Reverse bytes in each halfword
Reverse bytes in bottom halfword and sign-extend
Rotate right by number in register
Subtract a register value from an immediate 12-bit value
Subtract a register value from a shifted register value
Subtract immediate 12-bit value and C bit from register value
Subtract shifted register value and C bit from register value
Copy selected bits to register and sign-extend
Signed divide
Send event
Multiply signed halfwords and add signed-extended value to
2-register value
Multiply two signed register values
Signed saturate
1-20
Table 1-2 32-bit Cortex-M3 instruction summary (continued)
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Assembler
MOVW.W <Rd>, #<immed_16>
MRS<c> <Rd>, <psr>
MSR<c> <psr>_<fields>,<Rn>
MUL.W <Rd>, <Rn>, <Rm>
NOP.W
ORN{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
ORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}
ORR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
ORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
RBIT.W <Rd>, <Rm>
REV.W <Rd>, <Rm>
REV16.W <Rd>, <Rn>
REVSH.W <Rd>, <Rn>
ROR{S}.W <Rd>, <Rn>, <Rm>
RSB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
RSB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
SBC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
SBC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
SBFX.W <Rd>, <Rn>, #<lsb>, #<width>
SDIV<c> <Rd>,<Rn>,<Rm>
SEV<c>
SMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
SMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
SSAT <c> <Rd>, #<imm>, <Rn>{, <shift>}
ARM DDI 0337B
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