Hitachi H8S/2318 Series Manuals

Manuals and User Guides for Hitachi H8S/2318 Series. We have 1 Hitachi H8S/2318 Series manual available for free PDF download: Hardware Manual

Hitachi H8S/2318 Series Hardware Manual (714 pages)

Brand: Hitachi | Category: Computer Hardware | Size: 2.65 MB

Table of Contents
5
Overview
18
Exception Handling
23
Overview
23
Exception Handling Types and Priority
23
Exception Handling Operation
24
Exception Vector Table
24
Reset
26
Overview
26
Reset Sequence
26
Interrupts after Reset
27
State of On-Chip Supporting Modules after Reset Release
27
Traces
28
Interrupts
29
Trap Instruction
30
Stack Status after Exception Handling
30
Notes on Use of the Stack
31
Interrupt Controller
32
Overview
32
Features
32
Block Diagram
33
Pin Configuration
34
Register Configuration
34
System Control Register (SYSCR)
34
Interrupt Priority Registers a to K (IPRA to IPRK)
36
IRQ Enable Register (IER)
37
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
38
IRQ Status Register (ISR)
39
Interrupt Sources
40
External Interrupts
40
Internal Interrupts
41
Interrupt Exception Vector Table
41
Interrupt Operation
45
Interrupt Control Modes and Interrupt Operation
45
Interrupt Control Mode 0
48
Interrupt Control Mode 2
51
Interrupt Exception Handling Sequence
52
Interrupt Response Times
54
Usage Notes
55
Contention between Interrupt Generation and Disabling
55
Instructions that Disable Interrupts
56
Times When Interrupts Are Disabled
56
Interrupts During Execution of EEPMOV Instruction
56
DTC and DMAC Activation by Interrupt
57
Overview
57
Block Diagram
57
Operation
58
Bus Controller
60
Overview
60
Features
60
Block Diagram
62
Pin Configuration
63
Register Configuration
64
Register Descriptions
65
Bus Width Control Register (ABWCR)
65
Access State Control Register (ASTCR)
66
Wait Control Registers H and L (WCRH, WCRL)
67
Bus Control Register H (BCRH)
70
Bus Control Register L (BCRL)
70
Memory Control Register (MCR)
75
DRAM Control Register (DRAMCR)
77
Refresh Timer Counter (RTCNT)
78
Refresh Time Constant Register (RTCOR)
79
Overview of Bus Control
79
Area Partitioning
79
Bus Specifications
81
Memory Interfaces
82
Advanced Mode
83
Chip Select Signals
84
Basic Bus Interface
85
Overview
85
Data Size and Data Alignment
85
Valid Strobes
87
Basic Timing
88
Wait Control
96
DRAM Interface
98
Overview
98
Setting DRAM Space
98
Address Multiplexing
98
Data Bus
99
Pins Used for DRAM Interface
99
Basic Timing
100
Precharge State Control
101
Wait Control
102
Byte Access Control
104
Burst Operation
106
Refresh Control
109
DMAC Single Address Mode and DRAM Interface
112
When DDS = 1
112
When DDS = 0
113
Burst ROM Interface
114
Overview
114
Basic Timing
114
Wait Control
116
Idle Cycle
117
Operation
117
Pin States in Idle Cycle
121
Write Data Buffer Function
122
Bus Release
123
Overview
123
Operation
123
Pin States in External Bus Released State
124
Transition Timing
125
Usage Note
126
Bus Arbitration
126
Overview
126
Operation
126
Bus Transfer Timing
127
External Bus Release Usage Note
127
Resets and the Bus Controller
127
DMA Controller
128
Overview
128
Features
128
Block Diagram
129
Overview of Functions
130
Pin Configuration
132
Register Configuration
133
Register Descriptions (1) (Short Address Mode)
134
Memory Address Registers (MAR)
135
I/O Address Register (IOAR)
136
Execute Transfer Count Register (ETCR)
136
DMA Control Register (DMACR)
137
DMA Band Control Register (DMABCR)
141
Register Descriptions (2) (Full Address Mode)
146
Memory Address Register (MAR)
146
I/O Address Register (IOAR)
146
Execute Transfer Count Register (ETCR)
147
DMA Control Register (DMACR)
148
DMA Band Control Register (DMABCR)
152
Register Descriptions (3)
157
DMA Write Enable Register (DMAWER)
157
DMA Terminal Control Register (DMATCR)
159
Module Stop Control Register (MSTPCR)
160
Operation
161
Transfer Modes
161
Sequential Mode
163
Idle Mode
166
Repeat Mode
169
Single Address Mode
173
Normal Mode
176
Block Transfer Mode
184
DMAC Activation Sources
185
Basic DMAC Bus Cycles
188
DMAC Bus Cycles (Dual Address Mode)
189
DMAC Bus Cycles (Single Address Mode)
197
Write Data Buffer Function
203
DMAC Multi-Channel Operation
204
Relation between the DMAC and External Bus Requests, Refresh Cycles, and the DTC
205
NMI Interrupts and DMAC
206
Forced Termination of DMAC Operation
207
Clearing Full Address Mode
208
Interrupts
209
Usage Notes
210
Data Transfer Controller
213
Overview
213
Features
213
Block Diagram
214
Register Configuration
215
Register Descriptions
216
DTC Mode Register a (MRA)
216
DTC Mode Register B (MRB)
218
DTC Source Address Register (SAR)
219
DTC Destination Address Register (DAR)
219
DTC Transfer Count Register a (CRA)
219
DTC Transfer Count Register B (CRB)
220
DTC Enable Registers (DTCER)
220
DTC Vector Register (DTVECR)
221
Module Stop Control Register (MSTPCR)
222
Operation
223
Overview
223
Activation Sources
227
DTC Vector Table
228
Location of Register Information in Address Space
231
Normal Mode
232
Repeat Mode
233
Block Transfer Mode
234
Chain Transfer
236
Operation Timing
237
Number of DTC Execution States
238
Procedures for Using DTC
240
Examples of Use of the DTC
241
Interrupts
246
Usage Notes
246
16-Bit Timer Pulse Unit (TPU)
247
Overview
247
Features
247
Block Diagram
251
Pin Configuration
252
Register Configuration
254
Register Descriptions
256
Timer Control Registers (TCR)
256
Timer Mode Registers (TMDR)
261
Timer I/O Control Registers (TIOR)
263
Timer Interrupt Enable Registers (TIER)
276
Timer Status Registers (TSR)
278
Timer Counters (TCNT)
282
Timer General Registers (TGR)
282
Timer Start Register (TSTR)
283
Timer Synchro Register (TSYR)
283
Module Stop Control Register (MSTPCR)
284
Interface to Bus Master
285
16-Bit Registers
285
Operation
287
Overview
287
Basic Functions
288
Synchronous Operation
294
Buffer Operation
296
Cascaded Operation
300
PWM Modes
302
Phase Counting Mode
307
Interrupts
314
Interrupt Sources and Priorities
314
DTC/DMAC Activation
316
A/D Converter Activation
316
Operation Timing
317
Input/Output Timing
317
Interrupt Signal Timing
321
Usage Notes
325
Programmable Pulse Generator (PPG)
335
Overview
335
Features
335
Block Diagram
336
Pin Configuration
337
Registers
338
Register Descriptions
339
Next Data Enable Registers H and L (NDERH, NDERL)
339
Output Data Registers H and L (PODRH, PODRL)
340
Next Data Registers H and L (NDRH, NDRL)
341
Notes on NDR Access
341
PPG Output Control Register (PCR)
343
PPG Output Mode Register (PMR)
345
Port 1 Data Direction Register (P1DDR)
347
Port 2 Data Direction Register (P2DDR)
348
Module Stop Control Register (MSTPCR)
348
Operation
349
Overview
349
Output Timing
350
Normal Pulse Output
351
Non-Overlapping Pulse Output
353
Inverted Pulse Output
356
Pulse Output Triggered by Input Capture
357
Usage Notes
358
Operation of Pulse Output Pins
358
Note on Non-Overlapping Output
358
Overview
360
Features
360
Block Diagram
361
Pin Configuration
362
Register Configuration
362
Timer Counters 0 and 1 (TCNT0, TCNT1)
363
Time Constant Registers A0 and A1 (TCORA0, TCORA1)
363
Time Constant Registers B0 and B1 (TCORB0, TCORB1)
364
Time Control Registers 0 and 1 (TCR0, TCR1)
364
Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
366
Module Stop Control Register (MSTPCR)
369
Operation
370
TCNT Incrementation Timing
370
Compare Match Timing
371
Timing of TCNT External Reset
373
Timing of Overflow Flag (OVF) Setting
373
Operation with Cascaded Connection
374
Interrupts
375
Interrupt Sources and DTC Activation
375
A/D Converter Activation
375
Sample Application
375
Usage Notes
376
Contention between TCNT Write and Clear
376
Contention between TCNT Write and Increment
377
Contention between TCOR Write and Compare Match
378
Contention between Compare Matches a and B
379
Switching of Internal Clocks and TCNT Operation
379
Interrupts and Module Stop Mode
381
Section 10 Watchdog Timer
382
Overview
382
Features
382
Block Diagram
383
Pin Configuration
384
Register Configuration
384
Timer Counter (TCNT)
384
Timer Control/Status Register (TCSR)
384
Reset Control/Status Register (RSTCSR)
387
Notes on Register Access
388
Operation
390
Operation in Watchdog Timer Mode
390
Operation in Interval Timer Mode
392
Timing of Overflow Flag (OVF) Setting
392
Timing of Watchdog Timer Overflow Flag (WOVF) Setting
393
Interrupts
393
Usage Notes
393
Contention between Timer Counter (TCNT) Write and Increment
393
Changing Value of CKS2 to CKS0
394
Switching between Watchdog Timer Mode and Interval Timer Mode
394
System Reset by WDTOVF Signal
395
Internal Reset in Watchdog Timer Mode
395
Section 11 Serial Communication Interface (SCI)
396
Overview
396
Features
396
Block Diagram
398
Pin Configuration
399
Register Configuration
400
Register Descriptions
401
Receive Shift Register (RSR)
401
Receive Data Register (RDR)
401
Transmit Shift Register (TSR)
402
Transmit Data Register (TDR)
402
Serial Mode Register (SMR)
403
Serial Control Register (SCR)
406
Serial Status Register (SSR)
410
Bit Rate Register (BRR)
413
Smart Card Mode Register (SCMR)
421
Module Stop Control Register (MSTPCR)
423
Operation
424
Overview
424
Operation in Asynchronous Mode
426
Multiprocessor Communication Function
437
Operation in Synchronous Mode
445
SCI Interrupts
454
Usage Notes
456
Section 12 Smart Card Interface
463
Overview
463
Features
463
Block Diagram
464
Register Descriptions
467
Smart Card Mode Register (SCMR)
467
Serial Status Register (SSR)
468
Serial Control Register (SCR)
471
Operation
472
Overview
472
Pin Connections
472
Data Format
474
Clock
478
Data Transfer Operations
480
Operation in GSM Mode
487
Operation in Block Transfer Mode
488
Usage Notes
488
Section 13 A/D Converter (8 Analog Input Channel Version)
492
Overview
492
Features
492
Block Diagram
493
Register Configuration
495
Register Descriptions
496
A/D Data Registers a to D (ADDRA to ADDRD)
496
A/D Control/Status Register (ADCSR)
497
Module Stop Control Register (MSTPCR)
500
Interface to Bus Master
501
Operation
502
Single Mode (SCAN = 0)
502
Scan Mode (SCAN = 1)
504
Input Sampling and A/D Conversion Time
506
Interrupts
508
Usage Notes
509
Section 14 A/D Converter (12 Analog Input Channel Version)
515
Overview
515
Features
515
Block Diagram
516
Pin Configuration
517
Register Configuration
518
A/D Control/Status Register (ADCSR)
518
A/D Control Register (ADCR)
518
Module Stop Control Register (MSTPCR)
523
Interface to Bus Master
524
Operation
525
Single Mode (SCAN = 0)
525
Scan Mode (SCAN = 1)
527
Input Sampling and A/D Conversion Time
529
External Trigger Input Timing
530
Interrupts
531
Usage Notes
532
Section 15 D/A Converter
534
Overview
534
Features
534
Block Diagram
535
Pin Configuration
536
Register Configuration
536
Register Descriptions
537
D/A Data Registers 0 to 3 (DADR0 to DADR3)
537
D/A Control Registers 01 and 23 (DACR01, DACR23)
537
Module Stop Control Register (MSTPCR)
539
Operation
540
Section 16 RAM
542
Overview
542
Block Diagram
542
System Control Register (SYSCR)
542
Operation
544
Usage Note
544
Section 17 ROM
545
Overview
545
Block Diagram
545
Register Configuration
546
Register Descriptions
546
Mode Control Register (MDCR)
546
Bus Control Register L (BCRL)
547
Operation
547
Overview of Flash Memory
550
Features
550
Overview
551
Flash Memory Operating Modes
552
On-Board Programming Modes
553
Flash Memory Emulation in RAM
555
Differences between Boot Mode and User Program Mode
556
Block Configuration
557
Pin Configuration
558
Register Configuration
559
Register Descriptions
560
Flash Memory Control Register 1 (FLMCR1)
560
Flash Memory Control Register 2 (FLMCR2)
563
Erase Block Register 1 (EBR1)
564
Erase Block Registers 2 (EBR2)
564
System Control Register 2 (SYSCR2)
565
RAM Emulation Register (RAMER)
566
On-Board Programming Modes
567
Boot Mode
568
User Program Mode
572
Programming/Erasing Flash Memory
574
Program Mode
574
Program-Verify Mode
575
Erase Mode
577
Erase-Verify Mode
577
Flash Memory Protection
579
Hardware Protection
579
Software Protection
579
Error Protection
580
Flash Memory Emulation in RAM
582
Emulation in RAM
582
RAM Overlap
583
Interrupt Handling When Programming/Erasing Flash Memory
584
Flash Memory PROM Mode
585
17.11.1 PROM Mode Setting
585
17.11.2 Socket Adapters and Memory Map
586
17.11.3 PROM Mode Operation
589
17.11.4 Memory Read Mode
590
Auto-Program Mode
590
Auto-Erase Mode
590
Status Read Mode
590
17.11.8 Status Polling
597
17.11.9 PROM Mode Transition Time
598
17.11.10 Notes on Memory Programming
598
Flash Memory Programming and Erasing Precautions
599
Section 18 Clock Pulse Generator
604
Overview
604
Block Diagram
604
Register Configuration
605
Register Descriptions
605
System Clock Control Register (SCKCR)
605
Oscillator
607
Connecting a Crystal Resonator
607
External Clock Input
609
Duty Adjustment Circuit
611
Medium-Speed Clock Divider
611
Bus Master Clock Selection Circuit
611
Section 19 Power-Down Modes
612
Overview
612
Register Configuration
613
Register Descriptions
614
Standby Control Register (SBYCR)
614
System Clock Control Register (SCKCR)
616
Module Stop Control Register (MSTPCR)
618
Medium-Speed Mode
619
Sleep Mode
620
Module Stop Mode
620
Usage Notes
621
Software Standby Mode
622
Clearing Software Standby Mode
622
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
623
Software Standby Mode Application Example
623
Usage Notes
624
Hardware Standby Mode
625
Hardware Standby Mode Timing
625
Clock Output Disabling Function
626
Appendix A Instruction Set
627
Instruction List
627
Instruction Codes
651
Operation Code Map
666
Number of States Required for Instruction Execution
670
Bus States During Instruction Execution
684
Condition Code Modification
698
Appendix B Internal I/O Registers
704
Addresses
704

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