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Hitachi H8/3814U Series Hardware Manual

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OMC932723300

H8/3814U Series

H8/3814U

HD6433814U

H8/3813U

HD6433813U

H8/3812U

HD6433812U

Hardware Manual

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Page 1 OMC932723300 H8/3814U Series H8/3814U HD6433814U H8/3813U HD6433813U H8/3812U HD6433812U Hardware Manual...
Page 2 A/D converter. This makes it ideal for use in systems requiring an LCD display. This manual describes the hardware of the H8/3814U Series. For details on the H8/3814U Series instruction set, refer to the H8/300L Series Programming Manual.
Page 3: Table Of Contents
Contents Section 1 Overview ......................Overview......................... Internal Block Diagram ....................Pin Arrangement and Functions ..................1.3.1 Pin Arrangement....................1.3.2 Pin Functions ...................... Section 2 ........................13 Overview......................... 13 2.1.1 Features....................... 13 2.1.2 Address Space..................... 14 2.1.3 Register Configuration..................14 Register Descriptions...................... 15 2.2.1 General Registers....................
Page 4 Memory Map ........................47 2.8.1 Memory Map ...................... 47 2.8.2 LCD RAM Address Relocation................48 Application Notes ......................49 2.9.1 Notes on Data Access ..................49 2.9.2 Notes on Bit Manipulation.................. 51 2.9.3 Notes on Use of the EEPMOV Instruction............57 Section 3 Exception Handling ..................
Page 5 5.3.1 Transition to Standby Mode ................100 5.3.2 Clearing Standby Mode ..................100 5.3.3 Oscillator Settling Time after Standby Mode is Cleared ........100 5.3.4 Transition to Standby Mode and Port Pin States ..........101 Watch Mode........................102 5.4.1 Transition to Watch Mode .................. 102 5.4.2 Clearing Watch Mode ..................
Page 6 8.3.2 Register Configuration and Description ............. 124 8.3.3 Pin Functions ...................... 128 8.3.4 Pin States ......................128 Port 3 ..........................129 8.4.1 Overview......................129 8.4.2 Register Configuration and Description ............. 129 8.4.3 Pin Functions ...................... 132 8.4.4 Pin States ......................133 8.4.5 MOS Input Pull-Up.....................
Page 7 8.11 Port A ..........................157 8.11.1 Overview......................157 8.11.2 Register Configuration and Description ............. 157 8.11.3 Pin Functions ...................... 159 8.11.4 Pin States ......................160 8.12 Port B ..........................161 8.12.1 Overview......................161 8.12.2 Register Configuration and Description ............. 161 8.13 Port C ..........................
Page 8 10.3 SCI3 ..........................218 10.3.1 Overview......................218 10.3.2 Register Descriptions..................221 10.3.3 Operation ......................239 10.3.4 Operation in Asynchronous Mode..............243 10.3.5 Operation in Synchronous Mode ..............251 10.3.6 Multiprocessor Communication Function ............258 10.3.7 Interrupts......................264 10.3.8 Application Notes ..................... 265 Section 11 A/D Converter ....................
Page 9 12.3.5 Boosting the LCD Driver Power Supply ............298 Section 13 H8/3814U Series Electrical Characteristics ........299 13.1 H8/3814U Series Absolute Maximum Ratings .............. 299 13.2 H8/3814U Series Electrical Characteristics..............300 13.2.1 Power Supply Voltage and Operating Range............ 300 13.2.2 DC Characteristics .................... 302 13.2.3 AC Characteristics ....................
Page 10: Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit) built around the high-speed H8/300L CPU core and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3814U Series features an on-chip liquid crystal display (LCD) controller/driver. Other on-chip peripheral functions include three timers, two serial communication interface channels, and an analog-to-digital (A/D) converter.
Page 11 Table 1-1 Features (cont) Item Description Typical instructions • Multiply (8 bits × 8 bits) • Divide (16 bits ÷ 8 bits) • Bit accumulator • Register-indirect designation of bit position Interrupts • 13 external interrupt pins: IRQ4 to IRQ0, WKP7 to WKP0 •...
Page 12 Table 1-1 Features (cont) Item Description Timers Three on-chip timers • Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (ø)* and four clock signals divided from the watch clock (ø •...
Page 13 Table 1-1 Features (cont) Item Specification Product lineup Product Code Mask ROM ZTAT™ Version Version Package ROM/RAM Size HD6433814UH — 100-pin QFP ROM: 32 kbytes (FP-100B) RAM: 512 bytes HD6433814UF — 100-pin QFP (FP-100A) HD6433813UH — 100-pin QFP ROM: 24 kbytes (FP-100B) RAM: 512 bytes HD6433813UF...
Page 14: Internal Block Diagram
1.2 Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3814U Series. /TMOW /TMOFL driver H8/300L /TMOFH power supply /TMIG Port 1 /COM Data bus (lower) /IRQ /COM /IRQ Port A /COM /IRQ /TMIF /COM /IRQ /ADTRG /SEG...
Page 15: Pin Arrangement And Functions
1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3814U Series pin arrangement is shown in figures 1-2 and 1-3. /SEG /SEG TEST /SEG /SEG /SEG /SEG /SEG /SEG /SEG /SEG /IRQ /ADTRG /SEG /SEG /SEG /SEG /SEG /SEG /SEG...
Page 16 PC /AN P1 /TMOW PC /AN PC /AN P9 /SEG /CL PC /AN P9 /SEG /CL P9 /SEG /DO TEST P9 /SEG /M P9 /SEG P9 /SEG P9 /SEG P9 /SEG P8 /SEG P8 /SEG P8 /SEG P2 /IRQ /ADTRG P8 /SEG P8 /SEG P8 /SEG...
Page 17: Pin Functions
1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3814U Series. Table 1-2 Pin Functions Pin No. Type Symbol FP-100B FP-100A Name and Functions Power 31, 76 34, 79 Input Power supply: All V pins should source pins...
Page 18 Table 1-2 Pin Functions (cont) Pin No. Type Symbol FP-100B FP-100A Name and Functions System Input Reset: When this pin is driven low, control the chip is reset Input Mode: This pin controls system clock oscillation in the reset state TEST Input Test: This is a test pin, not for use in...
Page 19 Table 1-2 Pin Functions (cont) Pin No. Type Symbol FP-100B FP-100A Name and Functions I/O ports 97 to 100 to Input Port B: This is an 8-bit input port 1, 100 to 4 to Input Port C: This is a 4-bit input port Input Port 4 (bit 3): This is a 1-bit input port...
Page 20 Table 1-2 Pin Functions (cont) Pin No. Type Symbol FP-100B FP-100A Name and Functions I/O ports 59 to 62 to Port 7: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7).
Page 21 Table 1-2 Pin Functions (cont) Pin No. Type Symbol FP-100B FP-100A Name and Functions 35 to 38 to Output LCD common output: controller/ These are LCD common output pins driver 75 to 78 to Output LCD segment output: These are LCD segment output pins Output LCD latch clock: This is the display data latch clock...
Page 22: Cpu
Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 23: Address Space
2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Page 24: Register Descriptions
2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
Page 25 Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions).
Page 26: Initial Register Values
2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
Page 27: Data Formats In General Registers
2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. Data Format 1-bit data don’t care 1-bit data don’t care Byte data don’t care Byte data don’t care Word data...
Page 28: Memory Data Formats
2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address.
Page 29: Addressing Modes
2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
Page 30 Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W.
Page 31: Effective Address Calculation
Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255).
Page 32 Table 2-2 Effective Address Calculation Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) Register direct, Rn Operand is contents of registers indicated by rm/rn Register indirect, @Rn Contents (16 bits) of register indicated by rm Register indirect with displacement, Contents (16 bits) of register @(d:16, Rn) indicated by rm...
Page 33 Table 2-2 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) Absolute address H'FF @aa:8 @aa:16 Immediate #xx:8 Operand is 1- or 2-byte immediate data #xx:16 Program-counter relative PC contents @(d:8, PC) Sign extension disp disp...
Page 34 Table 2-2 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) Memory indirect, @@aa:8 H'00 Memory contents (16 bits) Notation: rm, rn: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address...
Page 35: Instruction Set
2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Instructions Number Data transfer MOV, PUSH , POP Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT...
Page 36 Notation General register (destination) General register (source) General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 37: Data Transfer Instructions
2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 38 Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@–Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @–SP Notation: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 Data Transfer Instruction Codes...
Page 39: Arithmetic Operations
2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
Page 40: Logic Operations
2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction Size Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 41 Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Notation:...
Page 42: Bit Manipulations
2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 43 Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 44 BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand:...
Page 45 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Notation: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont)
Page 46: Branching Instructions
2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Function — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition...
Page 47 disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Notation: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes...
Page 48: System Control Instructions
2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* Function — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details Rs →...
Page 49: Block Data Transfer Instruction
RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Notation: Operation field Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction Size...
Page 50 Notation: Operation field Figure 2-10 Block Data Transfer Instruction Code...
Page 51: Basic Operational Timing
2.6 Basic Operational Timing CPU operation is synchronized by a system clock (ø) or a subclock (ø ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is called one state.
Page 52: Access To On-Chip Peripheral Modules
2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 53 Three-state access to on-chip peripheral modules Bus cycle state state state ø or ø Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access)
Page 54: Cpu States
2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep mode, standby mode, watch mode, and sub-sleep mode.
Page 55: Program Execution State
Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Exception- Exception- occurs handling handling request complete Program halt state Program execution state SLEEP instruction executed Figure 2-15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Page 56: Memory Map
2.8 Memory Map 2.8.1 Memory Map Figure 2-16 shows the H8/3814U Series memory map. H'0000 Interrupt vector area H'0029 H'002A On-chip ROM (16 kbytes) H'3FFF (24 kbytes) H'5FFF (32 kbytes) H'7FFF Reserved H'F740 LCD RAM (20 bytes) H'F753 Reserved H'FD80...
Page 57: Lcd Ram Address Relocation
2.8.2 LCD RAM Address Relocation After a reset, the LCD RAM area is located at addresses H'F740 to H'F753. However, this area can be relocated by setting the LCD RAM relocation register (RLCTR) bits. The LCD RAM relocation register is explained below. LCD RAM relocation register (RLCTR: H'FFCF) —...
Page 58: Application Notes
2.9 Application Notes 2.9.1 Notes on Data Access The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost.
Page 59 Access States Word Byte H'0000 Interrupt vector area (42 bytes) H'0029 H'002A On-chip ROM H8/3812U (16 kbytes) H'3FFF 32 kbytes H8/3813U (24 kbytes) H'5FFF H8/3814U (32 kbytes) H'7FFF — — — Reserved H'F740 LCD RAM (20 bytes) H'F753 Reserved — —...
Page 60: Notes On Bit Manipulation
As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. Count clock Timer counter Read Reload Write Timer load register Internal bus Figure 2-18 Timer Configuration Example This example does not apply to the on-chip timers in the H8/3814U Series.
Page 61 Example 2 Here a BSET instruction is executed designating port 3. and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P3 to high-level output.
Page 62 As a result of this operation, bit 0 in PDR3 becomes 1, and P3 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3.
Page 63 Bit manipulation in a register containing a write-only bit Example 3 In this example, the port 3 control register PCR3 is accessed by a BCLR instruction. As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 64 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR3 and BCLR instruction execution ends.
Page 65 [C: After executing BCLR] The work area (RAM0) value is written to PCR3. MOV. B @RAM0, R0L MOV. B R0L, @PCR3 Input/output Input Input Output Output Output Output Output Output Pin state High High level level level level level level level level PCR3...
Page 66: Notes On Use Of The Eepmov Instruction
Registers with write-only bits Register Name Abbreviation Address Port control register 1 PCR1 H'FFE4 Port control register 2 PCR2 H'FFE5 Port control register 3 PCR3 H'FFE6 Port control register 4 PCR4 H'FFE7 Port control register 5 PCR5 H'FFE8 Port control register 6 PCR6 H'FFE9 Port control register 7...
Page 67: Exception Handling
Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3814U Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Exception Handling Types and Priorities Priority...
Page 68 Reset exception handling takes place as follows. • The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. • The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC.
Page 69: Interrupt Immediately After Reset
Reset cleared Program initial instruction prefetch Vector fetch Internal processing ø 8,192 clock cycles Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3-2 Reset Sequence (when MD0 Pin is Low) 3.2.3 Interrupt Immediately after Reset After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,...
Page 70: Interrupts
3.3 Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP to WKP , IRQ to IRQ ), and 16 internal interrupts from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed.
Page 71 Table 3-2 Interrupt Sources and Priorities (cont) Vector Priority Interrupt Source Interrupt Number Vector Address High Timer A Timer A overflow H'0016 to H'0017 Timer FL Timer FL compare match H'001C to H'001D Timer FL overflow Timer FH Timer FH compare match H'001E to H'001F Timer FH overflow Timer G...
Page 72: Interrupt Control Registers
3.3.2 Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Interrupt Control Registers Register Name Abbreviation Initial Value Address IRQ edge select register IEGR H'E0 H'FFF2 Interrupt enable register 1 IENR1 H'00 H'FFF3 Interrupt enable register 2 IENR2 H'00 H'FFF4...
Page 73 Bit 3: IRQ edge select (IEG3) Bit 3 selects the input sensing of pin IRQ /TMIF. Bit 3 IEG3 Description Falling edge of IRQ /TMIF pin input is detected (initial value) Rising edge of IRQ /TMIF pin input is detected Bit 2: IRQ edge select (IEG2) Bit 2 selects the input sensing of pin IRQ...
Page 74 Interrupt enable register 1 (IENR1) IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA Description...
Page 75 Bits 4 to 0: IRQ to IRQ interrupt enable (IEN4 to IEN0) Bits 4 to 0 enable or disable IRQ to IRQ interrupt requests. Bit n IENn Description Disables interrupt request IRQ (initial value) Enables interrupt request IRQ (n = 4 to 0) 3.
Page 76 Bit 5: Reserved bit Bit 5 is reserved; it can be read and written. Bit 4: Timer G interrupt enable (IENTG) Bit 4 enables or disables timer G input capture and overflow interrupt requests. Bit 4 IENTG Description Disables timer G interrupts (initial value) Enables timer G interrupts Bit 3: Timer FH interrupt enable (IENTFH)
Page 77 Interrupt request register 1 (IRR1) IRRTA IRRS1 — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value Read/Write — Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A, SCI1, or IRQ to IRQ interrupt is requested.
Page 78 Bits 4 to 0: IRQ to IRQ interrupt request flags (IRRI4 to IRRI0) Bit n IRRIn Description Clearing conditions: (initial value) When IRRIn = 1, it is cleared by writing 0 to IRRIn. Setting conditions: IRRIn is set when pin IRQ is set to interrupt input, and the designated signal edge is detected.
Page 79 Bit 5: Reserved bit Bit 5 is reserved; it is always read as 0, and cannot be modified. Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG Description Clearing conditions: (initial value) When IRRTG = 1, it is cleared by writing 0 Setting conditions: When pin TMIG is set to TMIG input and the designated signal edge is detected Bit 3: Timer FH interrupt request flag (IRRTFH)
Page 80: External Interrupts
6. Wakeup interrupt request register (IWPR) IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible. IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP are set to wakeup input and a pin receives a falling edge input.
Page 81: Internal Interrupts
Interrupts IRQ to IRQ Interrupts IRQ to IRQ are requested by into pins inputs to IRQ to IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR). When these pins are designated as pins IRQ to IRQ in port mode registers 1 and 2 (PMR1 and...
Page 82: Interrupt Operations
3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-3 shows a block diagram of the interrupt controller. Figure 3-4 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Interrupt request External interrupts or internal interrupt enable...
Page 83 • The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. • If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack.
Page 84 Program execution state IRRIO = 1 IENO = 1 IRRI1 = 1 IEN1 = 1 IRRI2 = 1 IEN2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine Notation: Program counter...
Page 85 SP – 4 SP (R7) SP – 3 SP + 1 CCR* SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling exception handling...
Page 86 Interrupt is accepted Interrupt level Prefetch instruction of decision and wait for Instruction Internal Internal interrupt-handling routine Stack access Vector fetch end of instruction prefetch processing processing Interrupt request signal ø Internal address bus Internal read signal Internal write signal Internal data bus (10) (16 bits)
Page 87: Interrupt Response Time
3.3.6 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States Item States Waiting time for completion of executing instruction* 1 to 13 Saving of PC and CCR to stack Vector fetch...
Page 88: Application Notes
3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3834U Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 89: Notes On Rewriting Port Mode Registers
3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls these pins (IRQ to IRQ , and WKP...
Page 90 Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 (cont) Interrupt Request Flags Set to 1 Conditions IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP is low IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP is low IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP...
Page 91: Clock Pulse Generators
Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 92: System Clock Generator
4.2 System Clock Generator Clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. Connecting a crystal oscillator Figure 4-2 shows a typical method of connecting a crystal oscillator. Ω...
Page 93 Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator. Ω R = 1 M ±20% C = 30 pF ±10% C = 30 pF ±10% Ceramic oscillator: Murata Figure 4-4 Typical Connection to Ceramic Oscillator Notes on board design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points.
Page 94 External clock input method Connect an external clock signal to pin OSC1, and leave pin OSC open. Figure 4-6 shows a typical connection. External clock input Open Figure 4-6 External Clock Input (Example) Frequency Oscillator Clock (ø Duty cycle 45% to 55%...
Page 95: Subclock Generator
4.3 Subclock Generator Connecting a 32.768-kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 4.2.3 for the system clock. C = C = 15 pF (typ.) Figure 4-7 Typical Connection to 32.768-kHz Crystal Oscillator (Subclock)
Page 96 Inputting an external clock (1) Circuit configuration An external clock is input to the X pin. The X pin should be left open. An example of the connection in this case is shown in figure 4-9. External clock input Open Figure 4-9 Example of Connection when Inputting an External Clock (2) External clock Input a square waveform to the X...
Page 97 Table 4-2 DC Characteristics and Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless otherwise specified, including subactive mode) Values Applicable Item Symbol Unit Notes Input high voltage...
Page 98: Prescalers
4.4 Prescalers The H8/3814U Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Page 99: Note On Oscillators
4.5 Note on Oscillators Oscillator characteristics of both the masked ROM and ZTAT™ versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors.
Page 100: Power-Down Modes
Section 5 Power-Down Modes 5.1 Overview The H8/3814U Series has seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the seven operation modes. All but the active (high-speed) mode are power-down modes.
Page 101 Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal states in each mode. Program execution state Program halt state Reset state LSON = 0, MSON = 0 Program halt state Active (high-speed) mode SSBY = 1, TMA3 = 0, SSBY = 0, LSON = 0...
Page 102 Table 5-2 Internal State in Each Operation Mode Active Mode High Medium Sleep Watch Subactive Subsleep Standby Function Speed Speed Mode Mode Mode Mode Mode System clock oscillator Functions Functions Functions Halted Halted Halted Halted Subclock oscillator Functions Functions Functions Functions Functions Functions...
Page 103: System Control Registers
5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 System Control Register Name Abbreviation Initial Value Address System control register 1 SYSCR1 H'07 H'FFF0 System control register 2 SYSCR2 H'E0 H'FFF1 System control register 1 (SYSCR1)
Page 104 Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description Wait time = 8,192 states (initial value) Wait time = 16,384 states Wait time = 32,768 states Wait time = 65,536 states Wait time = 131,072 states Note: * Don’t care Bit 3: Low speed on flag (LSON) This bit chooses the system clock (ø) or subclock (ø...
Page 105 Bit 4 NESEL Description Sampling rate is ø Sampling rate is ø Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Page 106: Sleep Mode
Bits 1 and 0: Subactive mode clock select (SA1 and SA0) These bits select the CPU clock rate (ø /8, ø /4, or ø /2) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 Bit 0 Description ø...
Page 107: Standby Mode
5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer register A (TMA) is cleared to 0.
Page 108: Transition To Standby Mode And Port Pin States
• When an external clock is used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set. Table 5-3 Clock Frequency and Settling Time (times are in ms) STS2 STS1 STS0 Waiting Time 5 MHz 4 MHz...
Page 109: Watch Mode
5.4 Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules other than timer A and the LCD controller is halted.
Page 110: Subsleep Mode
5.5 Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1.
Page 111: Subactive Mode
5.6 Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, IRQ , or WKP to WKP interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer G, IRQ to IRQ , or WKP...
Page 112: Active (Medium-Speed) Mode
5.7 Active (medium-speed) Mode 5.7.1 Transition to Active (medium-speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ , or WKP to WKP interrupts in standby...
Page 113: Direct Transfer
5.8 Direct Transfer 5.8.1 Direct Transfer Overview The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1.
Page 114: Calculation Of Direct Transfer Time Before Transition
× tcyc before transition + number of states for interrupt exception handling execution × tcyc after transition ..(1) Example: Direct transfer time for the H8/3814U Series = (2 + 1) × 2tosc + 14 × 16tosc = 230 tosc Notation: tosc: OSC clock cycle time tcyc: System clock (ø) cycle time...
Page 115 × tcyc before transition + number of states for interrupt exception handling execution × tcyc after transition ..(2) Example: Direct transfer time for the H8/3814U Series = (2 + 1) × 16tosc + 14 × 2tosc = 76 tosc Notation: tosc: OSC clock cycle time tcyc: System clock (ø) cycle time...
Page 116 × tcyc after transition ..(4) Example: Direct transfer time for the H8/3814U Series (when CPU clock frequency is øw/8 and wait time is 8192 states) = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc...
Page 117: Rom
Even-numbered Odd-numbered address address Figure 6-1 ROM Block Diagram (H8/3814U) The H8/3814U Series does not include ZTAT™ versions*. The ZTAT™ versions* of the H8/3834U (HD6473834UH and HD6473834UF) may be used instead. Note: * ZTAT is a trademark of Hitachi, Ltd.
Page 118: Ram
Section 7 RAM 7.1 Overview The H8/3814U, H8/3813U and H8/3812U have 512 bytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram Figure 7-1 shows a block diagram of the on-chip RAM.
Page 119: I/O Ports
Section 8 I/O Ports 8.1 Overview The H8/3814U Series is provided with eight 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port, one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port. Table 8-1 indicates the functions of each port.
Page 120 Table 8-1 Port Functions (cont) Function Switching Port Description Pins Other Functions Register Port 3 • 8-bit I/O port to P3 None • Input pull-up MOS SCI1 data output (SO ), data PMR3 option input (SI ), clock input/output /SCK (SCK Port 4 •...
Page 121: Port 1
8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Figure 8-1 shows its pin configuration. P1 /IRQ /TMIF P1 /IRQ P1 /IRQ Port 1 P1 /TMIG P1 /TMOFH P1 /TMOFL P1 /TMOW Figure 8-1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration.
Page 122 Port data register 1 (PDR1) Initial value Read/Write PDR1 is an 8-bit register that stores data for pins P1 through P1 . If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Page 123 Port mode register 1 (PMR1) IRQ3 IRQ2 IRQ1 — TMIG TMOFH TMOFL TMOW Initial value Read/Write — PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'10. Bit 7: P1 /IRQ /TMIF pin function switch (IRQ3)
Page 124 Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. Bit 3: P1 /TMIG pin function switch (TMIG) This bit selects whether pin P1 /TMIG is used as P1 or as TMIG. Bit 3 TMIG Description...
Page 125: Pin Functions
8.2.3 Pin Functions Table 8-3 shows the port 1 pin functions. Table 8-3 Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 in PCR1.
Page 126 Table 8-3 Port 1 Pin Functions (cont) Pin Functions and Selection Method /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 in PCR1. TMIG PCR1 Pin function input pin P1 output pin TMIG input pin /TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR1 in PCR1.
Page 127: Pin States
8.2.4 Pin States Table 8-4 shows the port 1 pin states in each operating mode. Table 8-4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ /TMIF High- Retains Retains High- Retains Functional Functional /IRQ impedance previous previous impedance* previous /IRQ...
Page 128: Port 2
8.3 Port 2 8.3.1 Overview Port 2 is an 8-bit I/O port. Figure 8-2 shows its pin configuration. Port 2 P2 /IRQ /ADTRG Figure 8-2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8-5 shows the port 2 register configuration. Table 8-5 Port 2 Registers Name Abbrev.
Page 129 1. Port data register 2 (PDR2) Initial value Read/Write PDR2 is an 8-bit register that stores data for pins P2 through P2 . If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read.
Page 130 Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: TMIG noise canceller select (NCS) This bit controls the noise canceller circuit for input capture at pin TMIG. Bit 4 Description Noise canceller function not selected...
Page 131 Bit 1: Reserved bit Bit 1 is reserved; it is always read as 1, and cannot be modified. Bit 0: P2 /IRQ /ADTRG pin function switch (IRQ4) This bit selects whether pin P2 /IRQ /ADTRG is used as P2 or as IRQ /ADTRG.
Page 132: Pin Functions
8.3.3 Pin Functions Table 8-6 shows the port 2 pin functions. Table 8-6 Port 2 Pin Functions Pin Functions and Selection Method to P2 Input or output is selected as follows by the bit settings in PCR2. (n = 1 to 7) PCR2n Pin function input pin...
Page 133: Port 4
8.4 Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8-3. Port 3 P3 /SO P3 /SI P3 /SCK Figure 8-3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8-8 shows the port 3 register configuration. Table 8-8 Port 3 Registers Name Abbrev.
Page 134 Port data register 3 (PDR3) Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Page 135 4. Port mode register 3 (PMR3) — — — — — SCK1 Initial value Read/Write — — — — — PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'F8. Bit 7 to 3: Reserved bits Bit 7 to 3 are reserved;...
Page 136: Pin Functions
8.4.3 Pin Functions Table 8-9 shows the port 3 pin functions. Table 8-9 Port 3 Pin Functions Pin Functions and Selection Method to P3 Input or output is selected as follows by the bit settings in PCR3. (n = 3 to 7) PCR3n Pin function input pin...
Page 137: Pin States
8.4.4 Pin States Table 8-10 shows the port 3 pin states in each operating mode. Table 8-10 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active to P3 High- Retains Retains High- Retains Functional Functional impedance previous previous impedance* previous state...
Page 138: Port 5
8.5 Port 4 8.5.1 Overview Port 4 consists of a 3-bit I/O port and a 1-bit input port, and is configured as shown in figure 8-4. P4 /IRQ P4 /TXD Port 4 P4 /RXD P4 /SCK Figure 8-4 Port 4 Pin Configuration 8.5.2 Register Configuration and Description Table 8-11 shows the port 4 register configuration.
Page 139 1. Port data register 4 (PDR4) — — — — Initial value Read/Write — — — — PDR4 is an 8-bit register that stores data for port 4 pins P4 to P4 . If port 4 is read while PCR4 bit are set to 1, the values stored in PDR4 are read, regardless of the actual pin states.
Page 140: Pin Functions
8.5.3 Pin Functions Table 8-12 shows the port 4 pin functions. Table 8-12 Port 4 Pin Functions Pin Functions and Selection Method /IRQ The pin function depends on the IRQ0 bit setting in PMR2. IRQ0 Pin function input pin input pin /TXD The pin function depends on bit TE in SCR3 and bit PCR4 in PCR4.
Page 141: Pin States
8.5.4 Pin States Table 8-13 shows the port 4 pin states in each operating mode. Table 8-13 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ High- Retains Retains High- Retains Functional Functional /TXD impedance previous previous impedance previous...
Page 142: Port 6
8.6 Port 5 8.6.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8-5. P5 /WKP /SEG P5 /WKP /SEG P5 /WKP /SEG P5 /WKP /SEG Port 5 P5 /WKP /SEG P5 /WKP /SEG P5 /WKP /SEG P5 /WKP /SEG Figure 8-5 Port 5 Pin Configuration 8.6.2 Register Configuration and Description...
Page 143 1. Port data register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 144 4. Port mode register 5 (PMR5) WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial value Read/Write PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5 /WKP /SEG...
Page 145: Pin Functions
8.6.3 Pin Functions Table 8-15 shows the port 5 pin functions. Table 8-15 Port 5 Pin Functions Pin Functions and Selection Method /WKP The pin function depends on bit WKPn in PMR5, bit PCR5 in PCR5, and bits to P5 SGS3 to SGS0 in LPCR.
Page 146: Pin States
8.6.4 Pin States Table 8-16 shows the port 5 pin states in each operating mode. Table 8-16 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /WKP High- Retains Retains High- Retains Functional Functional to P5 / impedance previous previous impedance* previous /SEG...
Page 147: Port 7
8.7 Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port, configured as shown in figure 8-6. P6 /SEG P6 /SEG P6 /SEG P6 /SEG Port 6 P6 /SEG P6 /SEG P6 /SEG P6 /SEG Figure 8-6 Port 6 Pin Configuration 8.7.2 Register Configuration and Description Table 8-17 shows the port 6 register configuration.
Page 148 Port data register 6 (PDR6) Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 . If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Page 149: Pin Functions
8.7.3 Pin Functions Table 8-18 shows the port 6 pin functions. Table 8-18 Port 6 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR6 in PCR6 and bits SGS3 to SGS0 in /SEG LPCR. (n = 7 to 4) SGS3 to SGS0 00** or 010*...
Page 150 8.7.5 MOS Input Pull-Up Port 6 has a built-in MOS input pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin.
Page 151: Port 8
8.8 Port 7 8.8.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8-7. P7 /SEG P7 /SEG P7 /SEG P7 /SEG Port 7 P7 /SEG P7 /SEG P7 /SEG P7 /SEG Figure 8-7 Port 7 Pin Configuration 8.8.2 Register Configuration and Description Table 8-20 shows the port 7 register configuration.
Page 152 Port data register 7 (PDR7) Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Page 153: Pin Functions
8.8.3 Pin Functions Table 8-21 shows the port 7 pin functions. Table 8-21 Port 7 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR7 in PCR7 and bits SGS3 to SGS0 in /SEG LPCR. (n = 7 to 4) SGS3 to SGS0 00**...
Page 154: Port 9
8.9 Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8-9. P8 /SEG P8 /SEG P8 /SEG P8 /SEG Port 8 P8 /SEG P8 /SEG P8 /SEG P8 /SEG Figure 8-8 Port 8 Pin Configuration 8.9.2 Register Configuration and Description Table 8-23 shows the port 8 register configuration.
Page 155 Port data register 8 (PDR8) Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P8 to P8 . If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Page 156: Pin Functions
8.9.3 Pin Functions Table 8-24 shows the port 8 pin functions. Table 8-24 Port 8 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR8 in PCR8 and bits SGS3 to SGS0 in /SEG LPCR. (n = 7 to 4) SGS3 to SGS0 000*...
Page 157 8.10 Port 9 8.10.1 Overview Port 9 is an 8-bit I/O port configured as shown in figure 8-9. P9 /SEG P9 /SEG P9 /SEG P9 /SEG Port 9 P9 /SEG P9 /SEG P9 /SEG P9 /SEG Figure 8-9 Port 9 Pin Configuration 8.10.2 Register Configuration and Description Table 8-26 shows the port 9 register configuration.
Page 158 Port data register 9 (PDR9) Initial value Read/Write PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
Page 159 8.10.3 Pin Functions Table 8-27 shows the port 9 pin functions. Table 8-27 Port 9 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR9 in PCR9, and bits SGX and SGS3 to SGS0 in LPCR. SGS3 to SGS0 0000 Not 0000...
Page 160 Table 8-27 Port 9 Pin Functions (cont) Pin Functions and Selection Method /SEG The pin function depends on bit PCR9 in PCR9 and bits SGS3 to SGS0 in /SEG LPCR. (n = 3 to 0) SGS3 to SGS0 0000 Not 0000 PCR9 Pin function input pin P9...
Page 161 8.11 Port A 8.11.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8-10. PA /COM PA /COM Port A PA /COM PA /COM Figure 8-10 Port A Pin Configuration 8.11.2 Register Configuration and Description Table 8-29 shows the port A register configuration. Table 8-29 Port A Registers Name Abbrev.
Page 162 Port data register A (PDRA) — — — — Initial value Read/Write — — — — PDRA is an 8-bit register that stores data for port A pins PA to PA . If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read.
Page 163 8.11.3 Pin Functions Table 8-30 gives the port A pin functions. Table 8-30 Port A Pin Functions Pin Functions and Selection Method /COM The pin function depends on bit PCRA in PCRA and bits DTS1, DTS0, CMX, SGX, and SGS3 to SGS0 in LPCR. DTS1,DTS0 Not 11 Not 11...
Page 164: Pin States
Table 8-30 Port A Pin Functions (cont) Pin Functions and Selection Method /COM The pin function depends on bit PCRA in PCRA, and bits SGX and SGS3 to SGS0 in LPCR. SGS3 to SGS0 0000 0000 Not 0000 PCRA Pin function input pin PA output pin output pin...
Page 165: Port B
8.12 Port B 8.12.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8-11. PB /AN PB /AN PB /AN PB /AN Port B PB /AN PB /AN PB /AN PB /AN Figure 8-11 Port B Pin Configuration 8.12.2 Register Configuration and Description Table 8-32 shows the port B register configuration.
Page 166: Port C
8.13 Port C 8.13.1 Overview Port C is a 4-bit input-only port, configured as shown in figure 8-12. PC /AN PC /AN Port C PC /AN PC /AN Figure 8-12 Port C Pin Configuration 8.13.2 Register Configuration and Description Table 8-33 shows the port C register configuration. Table 8-33 Port C Register Name Abbrev.
Page 167: Timers
Section 9 Timers 9.1 Overview The H8/3814U Series provides three timers (timers A, F, and G) on-chip. Table 9-1 outlines the functions of timers A, F, and G. Table 9-1 Timer Functions Event Waveform Name Functions Internal Clock Input Pin Output Pin Remarks Timer A •...
Page 168: Timer A
9.2 Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. Features Features of timer A are given below.
Page 169 2. Block diagram Figure 9-2-1 shows a block diagram of timer A. ø ø /4 ø /32 ø /16 ø /8 ø /4 ø /128 TMOW ø/32 ø/8192, ø/4096, ø/2048, ø/16 ø/512, ø/256, ø/128, ø/8 ø/32, ø/8 ø/4 ø IRRTA Notation: TMA: Timer mode register A...
Page 170: Register Descriptions
4. Register configuration Table 9-2-2 shows the register configuration of timer A. Table 9-2-2 Timer A Registers Name Abbrev. Initial Value Address Timer mode register A H'10 H'FFB0 Timer counter A H'00 H'FFB1 9.2.2 Register Descriptions 1. Timer mode register A (TMA) TMA7 TMA6 TMA5...
Page 171 Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 Bit 2...
Page 172: Timer Operation
2. Timer counter A (TCA) TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA).
Page 173: Timer A Operation States
Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available.
Page 174: Timer F
9.3 Timer F 9.3.1 Overview Timer F is a 16-bit timer with an output compare function. Compare match signals can be used to reset the counter, request an interrupt, or toggle the output. Timer F can also be used for external event counting, and can operate as two independent 8-bit timers, timer FH and timer FL.
Page 175 2. Block diagram Figure 9-3-1 shows a block diagram of timer F. ø IRRTFL TCRF TCFL TMIF Toggle TMOFL Compare circuit circuit OCRFL TCFH Toggle TMOFH Match Compare circuit circuit OCRFH TCSRF IRRTFH Notation: TCRF: Timer control register F TCSRF: Timer control status register F TCFH: 8-bit timer counter FH...
Page 176: Register Descriptions
3. Pin configuration Table 9-3-1 shows the timer F pin configuration. Table 9-3-1 Pin Configuration Name Abbrev. Function Timer F event input TMIF Input Event input to TCFL Timer FH output TMOFH Output Timer FH output Timer FL output TMOFL Output Timer FL output 4.
Page 177 TCF is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, TCFH and TCFL. TCF can be used as a 16-bit counter, with TCFH as the upper 8 bits and TCFL as the lower 8 bits of the counter, or TCFH and TCFL can be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP).
Page 178 2. 16-bit output compare register (OCRF) 8-bit output compare register (OCRFH) 8-bit output compare register (OCRFL) OCRF Initial value Read/Write OCRFH OCRFL OCRF is a 16-bit read/write output compare register consisting of two 8-bit read/write registers OCRFH and OCRFL. It can be used as a 16-bit output compare register, with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as independent 8-bit registers.
Page 179 The output at pin TMOFH (TMOFL) can be toggled by compare match. The output level can also be set to high or low by bit TOLH (TOLL) of the timer control register (TCRF). 3. Timer control register F (TCRF) TOLH CKSH2 CKSH1 CKSH0...
Page 180 Bit 3: Toggle output level L (TOLL) Bit 3 sets the output level at pin TMOFL. The setting goes into effect immediately after this bit is written. Bit 3 TOLL Description Low level (initial value) High level Bits 2 to 0: Clock select L (CKSL2 to CKSL0) Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input.
Page 181 Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating TCFH overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH Description Clearing conditions: (initial value) After reading OVFH = 1, cleared by writing 0 to OVFH Setting conditions:...
Page 182 Bit 4: Counter clear H (CCLRH) In 16-bit mode, bit 4 selects whether or not TCF is cleared when a compare match occurs between TCF and OCRF. In 8-bit mode, bit 4 selects whether or not TCFH is cleared when a compare match occurs between TCFH and OCRFH.
Page 183: Interface With The Cpu
Bit 1: Timer overflow interrupt enable L (OVIEL) Bit 1 enables or disables TCFL overflow interrupts. Bit 1 OVIEL Description TCFL overflow interrupt disabled (initial value) TCFL overflow interrupt enabled Bit 0: Counter clear L (CCLRL) Bit 0 selects whether or not TCFL is cleared when a compare match occurs between TCFL and OCRFL.
Page 184 • Read access When the upper byte of TCF is read, the upper-byte data is sent directly to the CPU, and the lower byte is loaded into TEMP. Next when the lower byte is read, the lower byte in TEMP is sent to the CPU.
Page 185 Upper byte write Internal data bus (H'AA) TEMP (H'AA) TCFH TCFL Lower byte write Internal data bus (H'55) TEMP (H'AA) TCFH TCFL (H'AA) (H'55) Figure 9-3-2 TCF Write Operation (CPU → TCF)
Page 186 Upper byte read Internal data bus (H'AA) TEMP (H'FF) TCFH TCFL (H'AA) (H'FF) Lower byte read Internal data bus (H'FF) TEMP (H'FF) TCFH TCFL (AB) (00) Note: Becomes H'AB00 if counter is incremented once. Figure 9-3-3 TCF Read Operation (TCF → CPU)
Page 187: Timer Operation
9.3.4 Timer Operation Timer F is a 16-bit timer/counter that increments with each input clock. When the value set in output compare register F matches the count in timer F, the timer can be cleared, an interrupt can be requested, and the port output can be toggled. Timer F can also be used as two independent 8-bit timers.
Page 188 • 8-bit timer mode When the CKSH2 bit in TCRF is set to 1, timer F operates as two independent 8-bit timers, TCFH and TCFL. The input clock of TCFH/TCFL is selected by bits CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When TCFH/TCFL and the contents of OCRFH/OCRFL match, the CMFH/CMFL bit in TCSRF is set to 1.
Page 189 3. TMOFH and TMOFL output timing The outputs at pins TMOFH and TMOFL are the values set in bits TOLH and TOLL in TCRF. When a compare match occurs, the output value is inverted. Figure 9-3-4 shows the output timing. ø...
Page 190: Application Notes
Timer F operation states Table 9-3-3 summarizes the timer F operation states. Table 9-3-3 Timer F Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby Reset Functions Functions Halted Halted Halted Halted OCRF Reset Functions Retained Retained Retained Retained...
Page 191 8-bit timer mode TCFH and OCRFH The output at pin TMOFH toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH.
Page 192: Timer G
9.4 Timer G 9.4.1 Overview Timer G is an 8-bit timer, with input capture functions for separately capturing the rising edge and falling edge of pulses input at the input capture pin (input capture input signal). Timer G has a built-in noise canceller circuit that can eliminate high-frequency noise from the input capture signal, enabling accurate measurement of its duty cycle.
Page 193 2. Block diagram Figure 9-4-1 shows a block diagram of timer G. ø Level sense circuit ø /2 ICRGF Edge Noise sense canceller TMIG circuit circuit ICRGR IRRTG Notation: TMG: Timer mode register G TCG: Timer counter G ICRGF: Input capture register GF ICRGR: Input capture register GR IRRTG:...
Page 194: Register Descriptions
Register configuration Table 9-4-2 shows the register configuration of timer G. Table 9-4-2 Timer G Registers Name Abbrev. Initial Value Address Timer mode register G H'00 H'FFBC Timer counter G — H'00 — Input capture register GF ICRGF H'00 H'FFBD Input capture register GR ICRGR H'00...
Page 195 Input capture register GF (ICRGF) ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write ICRGF is an 8-bit read-only register. When the falling edge of the input capture signal is detected, the TCG value at that time is transferred to ICRGF. If the input capture interrupt select bit (IIEGS) is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1.
Page 196 Timer mode register G (TMG) OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value Read/Write Note: * Only 0 can be written, to clear flag. TMG is an 8-bit read/write register. It controls the choice of four input clocks, counter clear selection, and edge selection for input capture interrupt requests.
Page 197 Bit 5: Timer overflow interrupt enable (OVIE) Bit 5 enables or disables TCG overflow interrupts. Bit 5 OVIE Description TCG overflow interrupt disabled (initial value) TCG overflow interrupt enabled Bit 4: Input capture interrupt edge select (IIEGS) Bit 4 selects the input signal edge at which input capture interrupts are requested. Bit 4 IIEGS Description...
Page 198: Noise Canceller Circuit
9.4.3 Noise Canceller Circuit The noise canceller circuit built into the H8/3814U Series is a digital low-pass filter that rejects high-frequency pulse noise in the input at the input capture pin. The noise canceller circuit is enabled by the noise canceller select (NCS) bit in port mode register 2 (PMR2)*.
Page 199: Timer Operation
Note: * Rewriting the NCS bit may cause an internal input capture signal to be generated. Figure 9-4-3 shows a typical timing diagram for the noise canceller circuit. In this example, a high-level input at the input capture pin is rejected as noise because its pulse width is less than five sampling clock ø...
Page 200 TCG can be cleared to 0 at the rising edge, falling edge, or both edges of the input capture signal as determined with bits CCLR1 and CCLR0 of TMG. If TCG overflows while the input capture signal is high, bit OVFH of TMG is set. If TCG overflows while the input capture signal is low, bit OVFL of TMG is set.
Page 201 3. Timing of internal input capture signals • Timing with noise canceller function disabled Separate internal input capture signals are generated from the rising and falling edges of the external input signal. Figure 9-4-4 shows the timing of these signals. External input capture signal Internal input...
Page 202 4. Timing of input capture Figure 9-4-6 shows the input capture timing in relation to the internal input capture signal. Internal input capture signal N –1 N +1 Input capture H'XX register Figure 9-4-6 Input Capture Timing 5. TCG clear timing TCG can be cleared at the rising edge, falling edge, or both edges of the external input capture signal.
Page 203: Application Notes
6. Timer G operation states Table 9-4-3 summarizes the timer G operation states. Table 9-4-3 Timer G Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby Input Reset Functions* Functions* Halted Functions/ Functions/ Halted capture Halted* Halted* Interval Reset...
Page 204 Table 9-4-4 Internal Clock Switching and TCG Operation Clock Level Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from low level to Clock before switching low level Clock after switching Count clock N +1 CKS bits modified Goes from low level to Clock before high level...
Page 205 2. Note on rewriting port mode registers When a port mode register setting is modified to enable or disable the input capture function or input capture noise canceling function, note the following points. • Switching the function of the input capture pin When the function of the input capture pin is switched by modifying the TMIG bit in port mode register 1 (PMR1), an input capture edge may be recognized even though no valid signal edge has been input.
Page 206 If switching of the pin function generates a false input capture edge matching the edge selected by the input capture interrupt edge select bit (IIEGS), the interrupt request flag will be set to 1, making it necessary to clear this flag to 0 before using the interrupt function. Figure 9-4-8 shows the procedure for modifying port mode register settings and clearing the interrupt request flag.
Page 207: Sample Timer G Application
9.4.6 Sample Timer G Application The absolute values of the high and low widths of the input capture signal can be measured by using timer G. The CCLR1 and CCLR0 bits of TMG should be set to 1. Figure 9-4-9 shows an example of this operation.
Page 208: Serial Communication Interface
Section 10 Serial Communication Interface 10.1 Overview The H8/3814U Series is provided with a two-channel serial communication interface (SCI). Table 10-1-1 summarizes the functions and features of the two SCI channels. Table 10-1-1 Serial Communication Interface Functions Channel Functions Features •...
Page 209: Sci1
10.2 SCI1 10.2.1 Overview Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. Features • Choice of 8-bit or 16-bit data length • Choice of eight internal clock sources (ø/1024, ø/256, ø/64, ø/32, ø/16, ø/8, ø/4, ø/2) or an external clock •...
Page 210 Block diagram Figure 10-2-1 shows a block diagram of SCI1. ø SCR1 Transmit/receive SCSR1 control circuit Transfer bit counter SDRU SDRL IRRS1 Notation: SCR1: Serial control register 1 SCSR1: Serial control/status register 1 SDRU: Serial data register U SDRL: Serial data register L IRRS1: SCI1 interrupt request flag PSS:...
Page 211: Register Descriptions
Pin configuration Table 10-2-1 shows the SCI1 pin configuration. Table 10-2-1 Pin Configuration Name Abbrev. Function SCI1 clock pin SCI1 clock input or output SCI1 data input pin Input SCI1 receive data input SCI1 data output pin Output SCI1 transmit data output Register configuration Table 10-2-2 shows the SCI1 register configuration.
Page 212 Bits 7 and 6: Operation mode select 1, 0 (SNC1, SNC0) Bits 7 and 6 select the operation mode. Bit 7 Bit 6 SNC1 SNC0 Description 8-bit synchronous transfer mode (initial value) 16-bit synchronous transfer mode Continuous clock output mode Reserved Notes: 1.
Page 213 Bits 2 to 0: Clock select (CKS2 to CKS 0) When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. Serial Clock Cycle Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Prescaler Division ø...
Page 214 Bit 6: Extended data bit (SOL) Bit 6 sets the SO output level. When read, SOL returns the output level at the SO pin. After completion of a transmission, SO continues to output the value of the last bit of transmitted data. The SO output can be changed by writing to SOL before or after a transmission.
Page 215 Bit 0: Start flag (STF) Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared to 0 upon completion of the transfer.
Page 216: Operation
4. Serial data register L (SDRL) SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0 Initial value Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Read/Write SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits).
Page 217 SO /SI Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 10-2-2 Transfer Format 3. Data transfer operations • Transmitting A transmit operation is carried out as follows. — Set bit SO in port mode register 3 (PMR3) to 1, making pin P3 the SO output pin.
Page 218 When an external clock is used, data is transmitted in synchronization with the serial clock input at pin SCK . After data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO can be changed by rewriting bit SOL in SCSR1.
Page 219 • Simultaneous transmit/receive A simultaneous transmit/receive operation is carried out as follows. — Set bits SO , SI , and SCK1 in PMR3 to 1, making pin P3 the SO output pin, pin the SI input pin, and pin P3 /SCK the SCK I/O pin.
Page 220: Interrupts
10.2.4 Interrupts SCI1 can generate an interrupt at the end of a data transfer. When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1 (IENR1).
Page 221: Sci3
10.3 SCI3 10.3.1 Overview Serial communication interface 3 (SCI3) has both synchronous and asynchronous serial data communication capabilities. It also has a multiprocessor communication function for serial data communication among two or more processors. Features SCI3 features are listed below. •...
Page 222 • Built-in baud rate generator with selectable bit rates. • Internal or external clock may be selected as the transfer clock source. • There are six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error. 2.
Page 223 Pin configuration Table 10-3-1 shows the SCI3 pin configuration. Table 10-3-1 Pin Configuration Name Abbrev. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output Register configuration Table 10-3-2 shows the SCI3 internal register configuration.
Page 224: Register Descriptions
10.3.2 Register Descriptions 1. Receive shift register (RSR) Read/Write — — — — — — — — The receive shift register (RSR) is for receiving serial data. Serial data is input in LSB-first order into RSR from pin RXD, converting it to parallel data. After each byte of data has been received, the byte is automatically transferred to the receive data register (RDR).
Page 225 3. Transmit shift register (TSR) Read/Write — — — — — — — — The transmit shift register (TSR) is for transmitting serial data. Transmit data is first transferred from the transmit data register (TDR) to TSR, then is transmitted from pin TXD, starting from the LSB (bit 0).
Page 226 5. Serial mode register (SMR) STOP CKS1 CKS0 Initial value Read/Write The serial mode register (SMR) is an 8-bit register for setting the serial data communication format and for selecting the clock source of the baud rate generator. SMR can be read and written by the CPU at any time.
Page 227 Bit 5: Parity enable (PE) In asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data and checked in received data. In synchronous mode there is no adding or checking of parity regardless of the setting here.
Page 228 Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop bit is not added, so this bit is ignored. Bit 3 STOP Description...
Page 229 Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0) Bits 1 and 0 select the clock source for the built-in baud rate generator. A choice of ø/64, ø/16, ø/4, or ø is made in these bits. See 8, Bit rate register, below for information on the clock source and bit rate register settings, and their relation to the baud rate.
Page 230 Bit 7: Transmit interrupt enable (TIE) Bit 7 enables or disables the transmit data empty interrupt (TXI) request when data is transferred from TDR to TSR and the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1. The TXI interrupt can be cleared by clearing bit TDRE to 0, or by clearing bit TIE to 0.
Page 231 Bit 4: Receive enable (RE) Bit 4 enables or disables the start of a receive operation. Bit 4 Description Receive operation disabled (RXD is a general I/O port) (initial value) Receive operation enabled (RXD is the receive data pin) Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and OER, which retain their states.
Page 232 Bit 2: Transmit end interrupt enable (TEIE) Bit 2 enables or disables the transmit end interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted. Bit 2 TEIE Description Transmit end interrupt (TEI) disabled (initial value) Transmit end interrupt (TEI) enabled* Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit...
Page 233 7. Serial status register (SSR) TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Note: Only 0 can be written for flag clearing. The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3 states, and containing the multiprocessor bits.
Page 234 Bit 6: Receive data register full (RDRF) Bit 6 is a status flag indicating whether there is receive data in RDR. Bit 6 RDRF Description Indicates there is no receive data in RDR (initial value) Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF. When data is read from RDR by an instruction.
Page 235 Bit 4: Framing error (FER) Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. Bit 4 Description Indicates that data receiving is in progress or has been completed (initial value) Clearing condition: After reading FER = 1, cleared by writing 0 to FER Indicates that a framing error occurred in data receiving Setting condition: The stop bit at the end of receive data is checked and found to be 0...
Page 236 Bit 2: Transmit end (TEND) Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified directly. Bit 2 TEND Description Indicates that transmission is in progress...
Page 237 Bit 0: Multiprocessor bit transmit (MPBT) Bit 0 holds the multiprocessor bit to be added to transmitted data when a multiprocessor format is used in asynchronous mode. Bit MPBT is ignored when synchronous mode is chosen, when the multiprocessor communication function is disabled, or when data transmission is disabled. Bit 0 MPBT Description...
Page 238 Table 10-3-3 BRR Settings and Bit Rates in Asynchronous Mode (1) OSC (MHz) 2.4576 4.194304 Bit Rate Error Error Error Error (bits/s) +0.03 +0.31 +0.03 –0.04 +0.16 +0.16 +0.21 +0.16 +0.16 +0.21 +0.16 +0.16 +0.21 1200 +0.16 +0.16 –0.70 2400 +0.16 +0.16 +1.14...
Page 239 Table 10-3-3 BRR Settings and Bit Rates in Asynchronous Mode (3) OSC (MHz) 9.8304 Bit Rate Error Error (bits/s) +0.31 –0.25 +0.16 +0.16 +0.16 1200 +0.16 2400 +0.16 4800 –1.36 9600 +1.73 19200 +1.73 31250 –1.70 38400 +1.73 Notes: 1. Settings should be made so that error is within 1%.
Page 240 The meaning of n is shown in table 10-3-4. Table 10-3-4 Relation between n and Clock SMR Setting Clock CKS1 CKS0 ø ø/4 ø/16 ø/64 Table 10-3-5 shows the maximum bit rate for selected frequencies in asynchronous mode. Values in table 10-3-5 are for active (high-speed) mode. Table 10-3-5 Maximum Bit Rate at Selected Frequencies (Asynchronous Mode) Setting OSC (MHz)
Page 241 Table 10-3-6 shows typical BRR settings in synchronous mode. Values in table 10-3-6 are for active (high-speed) mode. Table 10-3-6 Typical BRR Settings and Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) — — — — — — — —...
Page 242: Operation
The meaning of n is shown in table 10-3-7. Table 10-3-7 Relation between n and Clock SMR Setting Clock CKS1 CKS0 ø ø/4 ø/16 ø/64 10.3.3 Operation SCI3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses.
Page 243 Synchronous mode — Transfer format: 8 bits — Overrun error can be detected when data is received. — Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock, and outputs a serial clock.
Page 244 Table 10-3-9 SMR and SCR3 Settings and Clock Source Selection SCR3 Transmit/Receive Clock Bit7 Bit1 Bit0 Clock CKE1 CKE0 Mode Source Pin SCK Function Asynchronous Internal I/O port (SCK function not used) mode Outputs clock with same frequency as bit rate External Clock should be input with frequency 16 times the desired bit rate...
Page 245 ↑ RSR (receiving) (received and transferred) ← RDRF = 0 RDRF (RXI requested if RIE = 1) Figure 10-3-2 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) ↓ (transmission complete, TSR (transmitting) next data transferred) ← TDRE TDRE = 0 (TXI requested if TIE = 1) Figure 10-3-2 (b) TDRE Setting and TXI Interrupt TSR (transmitting)
Page 246: Operation In Asynchronous Mode
10.3.4 Operation in Asynchronous Mode In asynchronous communication mode, a start bit indicating the start of communication and a stop bit (1 or 2 bits) indicating the end of communication are added to each character that is sent. In this way synchronization is achieved for each character as a self-contained unit. SCI3 consists of independent transmit and receive modules, giving it the capability of full duplex communication.
Page 247 Table 10-3-11 shows the 12 formats that can be selected in asynchronous mode. The format is selected in the serial mode register (SMR). Table 10-3-11 Serial Communication Formats in Asynchronous Mode SMR Setting Serial Communication Format and Frame Length MP STOP 8-bit data STOP 8-bit data...
Page 248 2. Clock The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10-3-9 for the settings. Either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin SCK When an external clock source is input, it should have a frequency 16 times the desired bit rate.
Page 249 Figure 10-3-5 shows a typical flow chart for SCI3 initialization. Start Clear TE and RE to 0 in SCR3 Select the clock in serial control register 3 Set bits CKE1 and CKE0 (SCR3). If clock output is selected in asynchronous mode, a clock signal will be output as soon as CKE1 and CKE2 have been set.
Page 250 • Transmitting Figure 10-3-6 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR Read the serial status register (SRR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR).
Page 251 SCI3 operates as follows during data transmission in asynchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 252 • Receiving Figure 10-3-8 shows a typical flow chart for receiving serial data. After SCI3 initialization, follow the procedure below. Start 1. Read bits OER, PER, and FER in the serial status Read bits OER, PER, and register (SSR) to FER in SSR determine if a receive error has occurred.
Page 253 SCI3 operates as follows when receiving serial data in asynchronous mode. SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. The communication format for data receiving is as outlined in table 10-3-11.
Page 254: Operation In Synchronous Mode
Figure 10-3-9 shows a typical SCI3 data receive operation in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark data data (idle state) Serial data 1 frame 1 frame RDRF SCI3 operation RXI request RDRF cleared Detects stop bit = 0 to 0 ERI request due to framing error...
Page 255 Serial clock Don't Don't Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 care care 8 bits One unit of communication data (character or frame) Note: At high level except during continuous transmit/receive. Figure 10-3-10 Data Format in Synchronous Communication Mode In synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge.
Page 256 3. Data transmit/receive operations • SCI3 initialization Before transmitting or receiving data, follow the SCI3 initialization procedure explained under 10.3.4, SCI3 Initialization, and illustrated in figure 10-3-5. • Transmitting Figure 10-3-11 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below.
Page 257 SCI3 operates as follows during data transmission in synchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 258 • Receiving Figure 10-3-13 shows a typical flow chart for receiving data. After SCI3 initialization, follow the procedure below. Start 1. Read bit OER in the serial status register (SSR) Read bit OER in SSR to determine if an error has occurred. If an overrun error has occurred, overrun error processing is executed.
Page 259 SCI3 operates as follows when receiving serial data in synchronous mode. SCI3 synchronizes internally with the input or output of the serial clock and starts receiving. Received data is set in RSR from LSB to MSB. After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating that received data can be transferred from RSR to RDR.
Page 260 • Simultaneous transmit/receive Figure 10-3-15 shows a typical flow chart for transmitting and receiving simultaneously. After SCI3 synchronization, follow the procedure below. Read the serial status register (SSR), Start and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR).
Page 261: Multiprocessor Communication Function
Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, use the following procedure. • First confirm that TDRE and TEND are both set to 1 and that SCI3 has finished transmitting. Next clear TE to 0. Then set both TE and RE to 1. 2.
Page 262 Transmitting processor Communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID-sending cycle Data-sending cycle (receiving processor (data sent to receiving...
Page 263 • Transmitting multiprocessor data Figure 10-3-17 shows a typical flow chart for multiprocessor serial data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR Read the serial status register (SSR), and after confirming that bit TDRE = 1, set bit MPBT (multiprocessor bit transmit) in SSR to 0 or 1, then write transmit data in the TDRE = 1?
Page 264 SCI3 operates as follows during data transmission using a multiprocessor format. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 265 • Receiving multiprocessor data Figure 10-3-19 shows a typical flow chart for receiving data using a multiprocessor format. After SCI3 initialization, follow the procedure below. Start Set bit MPIE in SCR3 to 1 Set bit MPIE in serial control register 3 (SCR3) to 1. Read bits OER and FER in SSR Read bits OER and FER in the serial status register (SSR) to determine if an error has occurred.
Page 266 Figure 10-3-20 gives an example of data reception using a multiprocessor format. Start Receive Stop Start Receive Stop Mark data (ID1) data (data 1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value SCI3 operation RXI request RDRF cleared to 0 No RXI request MPIE cleared to 0 RDR state retained...
Page 267: Interrupts
10.3.7 Interrupts SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). All share a common interrupt vector. Table 10-3-13 describes each interrupt. Table 10-3-13 SCI3 Interrupts Interrupt Description Vector Address...
Page 268: Application Notes
10.3.8 Application Notes When using SCI3, attention should be paid to the following matters. 1. Relation between bit TDRE and writing data to TDR Bit TDRE in the serial status register (SSR) is a status flag indicating that TDR does not contain new transmit data.
Page 269 Break detection and processing Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set.
Page 270 16 clock cycles 8 clock cycles 15 0 Internal base clock Receive data Start bit (RXD) Synchronization sampling timing Data sampling timing Figure 10-3-21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be derived from the following equation. M = {(0.5 –...
Page 271 Relationship between bit RDRF and reading RDR While SCI3 is receiving, it checks the RDRF flag. When a frame of data has been received, if the RDRF flag is cleared to 0, data receiving ends normally. If RDRF is set to 1, an overrun error occurs.
Page 272 8. Switching SCK function If pin SCK is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock (ø) cycle immediately after it is switched.
Page 273: A/D Converter
Section 11 A/D Converter 11.1 Overview The H8/3814U Series includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 12 channels of analog input. 11.1.1 Features The A/D converter has the following features. • 8-bit resolution • 12 input channels •...
Page 274 11.1.3 Pin Configuration Table 11-1 shows the A/D converter pin configuration. Table 11-1 Pin Configuration Name Abbrev. Function Analog power supply pin Input Power supply and reference voltage of analog part Analog ground pin Input Ground and reference voltage of analog part Analog input pin 0 Input Analog input channel 0...
Page 275: Register Descriptions
11.2 Register Descriptions 11.2.1 A/D Result Register (ADRR) ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value — — — — — — — — Read/Write The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to- digital conversion.
Page 276 Bit 6: External trigger select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6 TRGE Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of the IRQ edge select register (IEGR).
Page 277: A/D Start Register (Adsr)
11.2.3 A/D Start Register (ADSR) ADSF — — — — — — — Initial value Read/Write — — — — — — — The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1.
Page 278: Operation
11.3 Operation 11.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1.
Page 279: Interrupts
11.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2).
Page 280 Interrupt (IRRAD) Set * IENAD Set * Set * A/D conversion starts ADSF Channel 1 (AN ) Idle A/D conversion (1) Idle A/D conversion (2) Idle operation state Read conversion result Read conversion result A/D conversion result (1) A/D conversion result (2) ADRR Note: ( ) indicates instruction execution by software.
Page 281 Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRR data Perform A/D conversion? Figure 11-4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software)
Page 282: Application Notes
Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRR data Perform A/D conversion? Figure 11-5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 11.6 Application Notes •...
Page 283: Lcd Controller/Driver
Section 12 LCD Controller/Driver 12.1 Overview The H8/3814U Series has an on-chip segment-type LCD controller circuit, LCD driver, and power supply circuit, for direct driving of an LCD panel. 12.1.1 Features Features of the LCD controller/driver are as follows. •...
Page 284: Block Diagram
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the LCD controller/driver. LCD driver power supply ø/2 to ø/256 Common Common ø data latch driver LPCR 40-bit Segment shift Display timing generator driver register LCD RAM 20 bytes SEG , DO Notation: LPCR: LCD port control register...
Page 285: Pin Configuration
12.1.3 Pin Configuration Table 12-1 shows the output pins assigned to the LCD controller/driver. Table 12-1 Pin Configuration Name Abbrev. Function LCD segment output Output Liquid crystal segment driver pins. All pins can be programmed also as ports. LCD common output Output Liquid crystal common driver pins.
Page 286 12.2 Register Descriptions 12.2.1 LCD Port Control Register (LPCR) DTS1 DTS0 SGS3 SGS0 SGS2 SGS1 Initial value Read/Write The LCD port control register is an 8-bit read/write register, used for selecting the duty cycle and the LCD driver and pin functions, etc. Upon reset, LPCR is initialized to H'00. Bits 7 to 5: Duty and common function select (DTS1, DTS0, CMX) Bits 7 to 6 select a driver duty of static, 1/2, 1/3, or 1/4.
Page 287 Bit 4: Expansion signal select (SGX) Bit 4 selects whether pins SEG , SEG , SEG /DO, and SEG /M are used as segment pins (SEG to SEG ) or as external segment expansion pins (CL , CL , DO, M). Bit 4 Description Pins SEG...
Page 288: Lcd Control Register (Lcr)
12.2.2 LCD Control Register (LCR) — DISP CKS3 CKS2 CKS1 CKS0 Initial value Read/Write — The LCD control register is an 8-bit read/write register for on/off control of the resistive voltage divider used as the LCD driver power supply, for display data control, and for frame frequency selection.
Page 289 Bit 4: Display data control (DISP) Bit 4 selects whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. This bit is valid also when the HD66100 is used for external segment expansion.
Page 290: Operation
• Large-panel display Because of the large impedance of the built-in resistive voltage divider, the H8/3814U Series LCD controller/driver is not well suited to driving large-panel displays. If use of a large panel leads to an unclear display, refer to 12.3.5 on boosting the LCD driver power supply. At static and 1/2 duty it is possible to boost the common output driving capacity.
Page 291: Relation Of Lcd Ram To Display
• Segment expansion The HD66100 can be connected externally to expand the number of segments. See 12.3.3, Connection to HD66100. Software settings • Duty cycle selection The duty cycle is selected in bits DTS1 and DTS0, with a choice of static, 1/2, 1/3, or 1/4 duty. •...
Page 292: Connection To Hd66100
Figure 12-10 shows typical connections to the HD66100. The output level is determined by the combination of data pins and pin M; but that combination differs between the H8/3814U Series and the HD66100. Table 12-3 shows the output level of the LCD driver power supply.
Page 293 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Internal driver display area Area not used for display H'F753 Note: Values immediately after reset. Figure 12-4 LCD RAM Map 2: No External Segment Expansion (1/3 Duty) Bit 7 Bit 6 Bit 5...
Page 294 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Internal driver display area H'F744 Area not used for display H'F753 Note: Values immediately after reset. Figure 12-6 LCD RAM Map 4: No External Segment Expansion (Static Duty) Bit 7 Bit 6 Bit 5...
Page 295 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 Internal driver display area H'F744 External driver display area H'F753 Note: Values immediately after reset. Figure 12-8 LCD RAM Map 2: External Segment Expansion (Static Duty) Bit 7 Bit 6 Bit 5...
Page 296 1/2 duty This LSI HD66100 Static This LSI HD66100 Figure 12-10 Connection to HD66100...
Page 297 1 frame Data Figure 12-11 (a) Waveforms at 1/4 Duty 1 frame Data Figure 12-11 (b) Waveforms at 1/3 Duty...
Page 298 1 frame Data V , V V , V Figure 12-11 (c) Waveforms at 1/2 Duty 1 frame Data Figure 12-11 (d) Waveforms at Static Duty...
Page 299: Operation In Power-Down Modes
Table 12-3 Output Levels Data Static Common output Segment output 1/2 duty Common output Segment output 1/3 duty Common output Segment output 1/4 duty Common output Segment output 12.3.4 Operation in Power-Down Modes The LCD controller/driver can be operated in the low-power modes, as shown in table 12-4. In the subactive, watch, and subsleep modes, the system clock pulse generator stops running, so no clock signal will be supplied and the display will be stopped, unless ø...
Page 300: Boosting The Lcd Driver Power Supply
12.3.5 Boosting the LCD Driver Power Supply When a large LCD panel is driven, or if segments are expanded externally, the built-in power supply capacity may be insufficient, making it necessary to lower the power supply impedance. One method, shown in figure 12-10, is to connect a bypass capacitor of around 0.1 µF to 0.3 µF to pins V , and V .
Page 301 Section 13 H8/3814U Series Electrical Characteristics 13.1 H8/3814U Series Absolute Maximum Ratings Table 13-1 lists the absolute maximum ratings. Table 13-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0...
Page 302: Power Supply Voltage And Operating Range
13.2 H8/3814U Series Electrical Characteristics 13.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3814U Series are indicated by the shaded region in the figures below. Power supply voltage vs. oscillator frequency range of H8/3814U Series 10.0...
Page 303 Subsleep mode (except CPU) • Watch mode (except CPU) 625.0 500.0 312.5 62.5 • Active mode (medium speed) Analog power supply voltage vs. A/D converter operating range of H8/3814U Series 625.0 500.0 312.5 62.5 • Active (high speed) mode •Active (medium speed) mode •...
Page 304: Dc Characteristics
13.2.2 DC Characteristics Table 13-2 lists the DC characteristics of the H8/3814U Series. Table 13-2 DC Characteristics of H8/3814U Series = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,...
Page 305 Table 13-2 DC Characteristics of H8/3814U Series (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, including subactive mode, unless otherwise indicated. Item Symbol...
Page 306 Table 13-2 DC Characteristics of H8/3814U Series (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, including subactive mode, unless otherwise indicated. Item Symbol...
Page 307 Table 13-2 DC Characteristics of H8/3814U Series (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, including subactive mode, unless otherwise indicated. Applicable Item...
Page 308 Table 13-2 DC Characteristics H8/3814U Series (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, including subactive mode, unless otherwise indicated. Applicable Item Symbol...
Page 309: Ac Characteristics
Table 13-3 lists the control signal timing, and tables 13-4 and 13-5 list the serial interface timing of the H8/3814U Series. Table 13-3 Control Signal Timing of H8/3814U Series = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T...
Page 310 Table 13-3 Control Signal Timing of H8/3814U Series (cont) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, including subactive mode, unless otherwise specified. Applicable...
Page 311 Table 13-5 Serial Interface (SCI3) Timing of H8/3814U Series = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Reference Item Symbol Min...
Page 312: A/D Converter Characteristics
13.2.4 A/D Converter Characteristics Table 13-6 shows the A/D converter characteristics of the H8/3814U Series. Table 13-6 A/D Converter Characteristics of H8/3814U Series = 2.7 V to 5.5 V, AV = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
Page 313: Lcd Characteristics
2. When V is supplied from an external source, the following relation must hold: V ≥ V Table 13-8 AC Characteristics for External Segment Expansion of H8/3814U Series = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T...
Page 314: Operation Timing
13.3 Operation Timing Figures 13-1 to 13-7 show timing diagrams. Figure 13-1 System Clock Input Timing Figure 13-2 RES Low Width IRQ to IRQ WKP to WKP ADTRG TMIF, TMIG Figure 13-3 Input Timing...
Page 315 scyc or V or V SCKL SCKH SCKf SCKr Notes: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 13-8. Figure 13-4 Serial Interface 1 Input/Output Timing...
Page 316 SCKW scyc Figure 13-5 SCK Input Clock Timing scyc or V or V (transmit data) (receive data) Notes: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 13-8. Figure 13-6 Input/Output Timing of Serial Interface 3 in Synchronous Mode...
Page 317 – 0.5 V 0.4 V – 0.5 V 0.4 V – 0.5 V 0.4 V 0.4 V Figure 13-7 Segment Expansion Signal Timing...
Page 318: Output Load Circuit
13.4 Output Load Circuit 2.4 kΩ Output pin 12 k Ω 30 pF Figure 13-8 Output Load Condition...
Page 319: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set A.1 Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 320 Table A-1 lists the H8/300L CPU instruction set. Table A-1 Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — 2 B Rs8 → Rd8 MOV.B Rs, Rd —...
Page 321 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C EEPMOV — if R4L≠0 then 4 — — — — — — Repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 →...
Page 322 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B Rd8 × Rs8 → Rd16 MULXU.B Rs, Rd — — — — — — 14 B Rd16÷Rs8 → Rd16 DIVXU.B Rs, Rd —...
Page 323 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C ROTL.B Rd — — ROTR.B Rd — — B (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — 2 B (#xx:3 of @Rd16) ←...
Page 324 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B (#xx:3 of Rd8) → Z BTST #xx:3, Rd — — — — — 2 B (#xx:3 of @Rd16) → Z BTST #xx:3, @Rd —...
Page 325 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Branching Mnemonic Operation Condition I H N Z V C B C∨(#xx:3 of @aa:8) → C BIOR #xx:3, @aa:8 — — — — — B C⊕(#xx:3 of Rd8) → C BXOR #xx:3, Rd —...
Page 326 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C — SP–2 → SP JSR @Rn — — — — — — 6 PC → @SP PC ← Rn16 — SP–2 → SP JSR @aa:16 —...
Page 327: Operation Code Map
A.2 Operation Code Map Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 328 Table A-2 Operation Code Map High SLEEP XORC ANDC ADDS ADDX SHLL SHLR ROTXL ROTXR SUBS SUBX SHAL SHAR ROTL ROTR MULXU DIVXU BIST BSET BNOT BCLR BTST BXOR BAND EEPMOV Bit-manipulation instructions BIOR BIXOR BIAND BILD ADDX SUBX Note: The PUSH and POP instructions are identical in machine language to MOV instructions.
Page 329: Number Of Execution States
A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates the number of cycles of each type occurring in each instruction.
Page 330 Table A-3 Number of Cycles in Each Instruction Access Location Execution Status (instruction cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access — Internal operation Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details.
Page 331 Table A-4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd...
Page 332 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd...
Page 333 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd...
Page 334 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B @(d:16, Rs), Rd 2 MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) 2 MOV.B Rs, @–Rd...
Page 335 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SHLL SHLL.B Rd SHAL SHAL.B Rd SHAR SHAR.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd...
Page 336: Appendix B On-Chip Registers
Appendix B On-Chip Registers B.1 I/O Registers (1) Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'A0 SCR1 SNC1 SNC0 — — CKS3 CKS2 CKS1 CKS0 SCI1...
Page 337 Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'BB OCRFL OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Timer F H'BC OVFH OVFL OVIE IIEGS CCLR1 CCLR0...
Page 338 Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'DE PDRB ports H'DF PDRC — — — — H'E0 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1...
Page 339: I/O Registers (2)
B.2 I/O Registers (2) Register Register Address to which the Name of acronym name register is mapped on-chip supporting module TMC—Timer mode register C H'B4 Timer C numbers Initial bit TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 values Names of the Initial value bits.
Page 340 SCR1—Serial control register 1 H'A0 SCI1 SNC1 SNC0 — — CKS3 CKS2 CKS1 CKS0 Initial value Read/Write Clock Select (CKS2 to CKS0) Serial Clock Cycle Bit 2 Bit 1 Bit 0 Synchronous Prescaler CKS2 CKS1 CKS0 Division ø = 5 MHz ø...
Page 341 SCSR1—Serial control/status register 1 H'A1 SCI1 — ORER — — — — Initial value Read/Write — R/(W) — — — — Start flag Read Indicates that transfer is stopped Write Invalid Read Indicates transfer in progress Write Starts a transfer operation Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0...
Page 342 SDRU—Serial data register U H'A2 SCI1 SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Initial value Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Read/Write Stores transmit and receive data 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data...
Page 343 SMR—Serial mode register H'A8 SCI3 STOP CKS1 CKS0 Initial value Read/Write Clock select 0, 1 ø clock Multiprocessor mode ø/4 clock 0 Multiprocessor communication function disabled ø/16 clock 1 Multiprocessor communication function enabled ø/64 clock Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity...
Page 344 SCR3—Serial control register 3 H'AA SCI3 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable Bit 1 Bit 0 Description CKE0 CKE1 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock Clock output...
Page 345 TDR—Transmit data register H'AB SCI3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write Data to be transferred to TSR...
Page 346 SSR—Serial status register H'AC SCI3 TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit receive Multiprocessor bit transmit 0 Indicates reception of data in which the multiprocessor bit is 0 0 The multiprocessor bit in transmit data is 0 1 Indicates reception of data in which the multiprocessor bit is 1 1 The multiprocessor bit in transmit data is 1 Transmit end...
Page 347 RDR—Receive data register H'AD SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write TMA—Timer mode register A H'B0 Timer A TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value Read/Write — Clock output select Internal clock select ø/32 Prescaler and Divider Ratio TMA3 TMA2...
Page 348 TCA—Timer counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write Count value TCRF—Timer control register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write Toggle output level H Clock select L 0 Low level External event (TMIF): Rising or falling edge...
Page 349 TCSRF—Timer control/status register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value Read/Write Timer overflow interrupt enable L 0 TCFL overflow interrupt disabled 1 TCFL overflow interrupt enabled Compare match flag L 0 [Clearing condition] After reading CMFL = 1, cleared by writing 0 to CMFL 1 [Setting condition] When the TCFL value matches the OCRFL value...
Page 350 TCFH—8-bit timer counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value Read/Write Count value TCFL—8-bit timer counter FL H'B9 Timer F TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL0 TCFL2 TCFL1 Initial value Read/Write Count value OCRFH—Output compare register FH H'BA Timer F...
Page 351 TMG—Timer mode register G H'BC Timer G OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value Read/Write R/(W) R/(W) Clock select Internal clock: ø/64 Internal clock: ø/32 Internal clock: ø/2 Internal clock: ø /2 Counter clear TCG is not cleared TCG is cleared at the falling edge of the input capture signal TCG is cleared at the rising edge of the input capture signal TCG is cleared at both edges of the input capture signal...
Page 352 ICRGF—Input capture register GF H'BD Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write ICRGR—Input capture register GR H'BE Timer G ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value Read/Write...
Page 353 LPCR—LCD port control register H'C0 LCD controller/driver DTS1 DTS0 SGS3 SGS2 SGS1 SGS0 Initial value Read/Write Segment driver select Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Functions of Pins SEG to SEG SEG to SEG to SGS3 SGS2 SGS1 SGS0...
Page 354 LCR—LCD control register H'C1 LCD controller/driver — DISP CKS3 CKS2 CKS1 CKS0 Initial value Read/Write — Frame frequency select Bit 3 Bit 2 Bit 1 Bit 0 Frame Frequency CKS3 CKS2 CKS1 CKS0 Clock ø = 5 MHz ø = 625 Hz ø...
Page 355 AMR—A/D mode register H'C4 A/D converter TRGE — — Initial value Read/Write — — Channel select Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected External trigger select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select...
Page 356 ADRR—A/D result register H'C5 A/D converter ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Read/Write A/D conversion result ADSR—A/D start register H'C6 A/D converter ADSF —...
Page 357 PMR1—Port mode register 1 H'C8 I/O ports IRQ3 IRQ2 IRQ1 — TMIG TMOFH TMOFL TMOW Initial value Read/Write — P1 /TMOW pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOW output pin P1 /TMOFL pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOFL output pin P1 /TMOFH pin function switch...
Page 358 PMR2—Port mode register 2 H'C9 I/O ports — — — IRQ0 POF1 — IRQ4 Initial value Read/Write — — — — P2 /IRQ /ADTRG pin function switch 0 Functions as P2 I/O pin 1 Functions as IRQ /ADTRG input pin P3 /SO pin PMOS control 0 CMOS output 1 NMOS open-drain output...
Page 359 PMR3—Port mode register 3 H'CA I/O ports — — — — — Initial value Read/Write — — — — — P3 /SCK pin function switch 0 Functions as P3 I/O pin 1 Functions as SCK I/O pin P3 /SI pin function switch 0 Functions as P3 I/O pin 1 Functions as SI input pin P3 /SO pin function switch...
Page 360 PMR4—Port mode register 4 H'CB I/O ports NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 Initial value Read/Write 0 P2 has CMOS output 1 P2 has NMOS open-drain output PMR5—Port mode register 5 H'CC I/O ports WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1...
Page 361 PDR1—Port data register 1 H'D4 I/O ports Initial value Read/Write PDR2—Port data register 2 H'D5 I/O ports Initial value Read/Write PDR3—Port data register 3 H'D6 I/O ports Initial value Read/Write PDR4—Port data register 4 H'D7 I/O ports — — — —...
Page 362 PDR6—Port data register 6 H'D9 I/O ports Initial value Read/Write PDR7—Port data register 7 H'DA I/O ports Initial value Read/Write PDR8—Port data register 8 H'DB I/O ports Initial value Read/Write PDR9—Port data register 9 H'DC I/O ports Initial value Read/Write PDRA—Port data register A H'DD I/O ports...
Page 363 PDRB—Port data register B H'DE I/O ports Initial value Read/Write PDRC—Port data register C H'DF I/O ports — — — — Initial value Read/Write — — — — PUCR1—Port pull-up control register 1 H'E0 I/O ports PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1...
Page 364 PUCR6—Port pull-up control register 6 H'E3 I/O ports PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 Initial value Read/Write PCR1—Port control register 1 H'E4 I/O ports PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 Initial value Read/Write Port 1 input/output select 0 Input pin 1 Output pin PCR2—Port control register 2...
Page 365 PCR3—Port control register 3 H'E6 I/O ports PCR3 PCR3 PCR3 PCR3 PCR3 PCR3 PCR3 PCR3 Initial value Read/Write Port 3 input/output select 0 Input pin 1 Output pin PCR4—Port control register 4 H'E7 I/O ports — — — — — PCR4 PCR4 PCR4...
Page 366 PCR6—Port control register 6 H'E9 I/O ports PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 Initial value Read/Write Port 6 input/output select 0 Input pin 1 Output pin PCR7—Port control register 7 H'EA I/O ports PCR7 PCR7 PCR7 PCR7 PCR7 PCR7 PCR7 PCR7...
Page 367 PCR9—Port control register 9 H'EC I/O ports PCR9 PCR9 PCR9 PCR9 PCR9 PCR9 PCR9 PCR9 Initial value Read/Write Port 9 input/output select 0 Input pin 1 Output pin PCRA—Port control register A H'ED I/O ports — — — — PCRA PCRA PCRA PCRA...
Page 368 SYSCR1—System control register 1 H'F0 System control SSBY STS2 STS1 STS0 LSON — — — Initial value Read/Write — — — Low speed on flag 0 The CPU operates on the system clock (ø) 1 The CPU operates on the subclock (ø Standby timer select 2 to 0 Wait time = 8,192 states Wait time = 16,384 states...
Page 369 SYSCR2—System control register 2 H'F1 System control — — — NESEL DTON MSON Initial value Read/Write — — — Medium speed on flag Subactive mode clock select 0 Operates in active (high-speed) mode ø /8 1 Operates in active (medium-speed) mode ø...
Page 370 IEGR—IRQ edge select register H'F2 System control — — — IEG4 IEG3 IEG2 IEG1 IEG0 Initial value Read/Write — — — IRQ edge select 0 Falling edge of IRQ pin input is detected 1 Rising edge of IRQ pin input is detected IRQ edge select 0 Falling edge of IRQ pin input is detected 1 Rising edge of IRQ pin input is detected...
Page 371 IENR1—Interrupt enable register 1 H'F3 System control IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write IRQ to IRQ interrupt enable 0 Disables interrupt request IRQ Enables interrupt request IRQ (n = 4 to 0) Wakeup interrupt enable 0 Disables interrupt requests from WKP to WKP Enables interrupt requests from WKP to WKP SCI1 interrupt enable...
Page 372 IENR2—Interrupt enable register 2 H'F4 System control IENDT IENAD — IENTG IENTFH IENTFL — — Initial value Read/Write Reserved bit Reserved bit Timer FL interrupt enable 0 Disables timer FL interrupts 1 Enables timer FL interrupts Timer FH interrupt enable 0 Disables timer FH interrupts 1 Enables timer FH interrupts Timer G interrupt enable...
Page 373 IRR1—Interrupt request register 1 H'F6 System control IRRTA IRRS1 — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value Read/Write — IRQ to IRQ interrupt request flag 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 1 [Setting condition] When pin IRQ is set to interrupt input and the designated signal edge is detected (n = 4 to 0)
Page 374 IRR2—Interrupt request register 2 H'F7 System control IRRDT IRRAD — IRRTG IRRTFH — IRRTFL — Initial value Read/Write Reserved bit Reserved bit Timer FL interrupt request flag 0 [Clearing condition] When IRRTFL = 1, it is cleared by writing 0 1 [Setting condition] When counter FL matches output compare register FL in 8-bit mode...
Page 375 IWPR—Wakeup interrupt request register H'F9 System control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write Wakeup interrupt request flag 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0 1 [Setting condition] When pin WKP is set to interrupt input and a falling signal edge is detected (n = 7 to 0) Note: Only a write of 0 for flag clearing is possible.
Page 376: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams C.1 Schematic Diagram of Port 1 SBY (low level during reset and in standby mode) Internal data bus PUCR1 PMR1 PDR1 PCR1 n – 4 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1:...
Page 377 Internal data bus PUCR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 Figure C-1 (b) Port 1 Block Diagram (Pin P1...
Page 378 Internal data bus PUCR1 PMR1 PDR1 PCR1 Timer G module TMIG PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C-1 (c) Port 1 Block Diagram (Pin P1...
Page 379 Timer F module TMOFH (P1 ) TMOFL (P1 ) Internal data bus PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 2, 1 Figure C-1 (d) Port 1 Block Diagram (Pins P1 and P1...
Page 380 Timer A module TMOW Internal data bus PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C-1 (e) Port 1 Block Diagram (Pin P1...
Page 381: Schematic Diagram Of Port 2
C.2 Schematic Diagram of Port 2 Internal data bus PMR4 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR4: Port mode register 4 n = 1 to 7 Figure C-2 (a) Port 2 Block Diagram (Pins P2 to P2...
Page 382 Internal data bus PMR4 PMR2 PDR2 PCR2 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C-2 (b) Port 2 Block Diagram (Pin P2...
Page 383: Schematic Diagram Of Port 3
C.3 Schematic Diagram of Port 3 Internal data bus PUCR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 n = 3 to 7 Figure C-3 (a) Port 3 Block Diagram (Pins P3 to P3...
Page 384 SCI1 module PMR2 Internal data bus PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PMR2: Port mode register 2 PUCR3: Port pull-up control register 3 Figure C-3 (b) Port 3 Block Diagram (Pin P3...
Page 385 Internal data bus PUCR3 PMR3 PDR3 PCR3 SCI1 module PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C-3 (c) Port 3 Block Diagram (Pin P3...
Page 386 SCI1 module EXCK SCKO SCKI PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C-3 (d) Port 3 Block Diagram (Pin P3...
Page 387: Schematic Diagram Of Port 4
C.4 Schematic Diagram of Port 4 Internal data bus PMR2 PMR2: Port mode register 2 Figure C-4 (a) Port 4 Block Diagram (Pin P4 SCI3 module PDR4 Internal data bus PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C-4 (b) Port 4 Block Diagram (Pin P4...
Page 388 SCI3 module PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C-4 (c) Port 4 Block Diagram (Pin P4...
Page 389 SCI3 module SCKIE SCKOE SCKO SCKI PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C-4 (d) Port 4 Block Diagram (Pin P4...
Page 390: Schematic Diagram Of Port 5
C.5 Schematic Diagram of Port 5 Internal data bus PUCR5 PMR5 PDR5 PCR5 PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 0 to 7 Figure C-5 Port 5 Block Diagram...
Page 391: Schematic Diagram Of Port 6
C.6 Schematic Diagram of Port 6 Internal data bus PUCR6 PDR6 PCR6 PDR6: Port data register 6 PCR6: Port control register 6 PUCR4: Port pull-up control register 6 n = 0 to 7 Figure C-6 Port 6 Block Diagram...
Page 392: Schematic Diagram Of Port 7
C.7 Schematic Diagram of Port 7 Internal data bus PDR7 PCR7 PDR7: Port data register 7 PCR7: Port control register 7 n = 0 to 7 Figure C-7 Port 7 Block Diagram...
Page 393: Schematic Diagram Of Port 8
C.8 Schematic Diagram of Port 8 Internal data bus PDR8 PCR8 PDR8: Port data register 8 PCR8: Port control register 8 n = 0 to 7 Figure C-8 Port 8 Block Diagram...
Page 394: Schematic Diagram Of Port 9
C.9 Schematic Diagram of Port 9 Internal data bus PDR9 PCR9 PDR9: Port data register 9 PCR9: Port control register 9 n = 0 to 7 Figure C-9 Port 9 Block Diagram...
Page 395: Schematic Diagram Of Port A
C.10 Schematic Diagram of Port A Internal data bus PDRA PCRA PDRA: Port data register A PCRA: Port control register A n = 0 to 3 Figure C-10 Port A Block Diagram...
Page 396: Schematic Diagram Of Port B
C.11 Schematic Diagram of Port B Internal data bus A/D module AMR to AMR n = 0 to 7 Figure C-11 Port B Block Diagram C.12 Schematic Diagram of Port C Internal data bus A/D module AMR to AMR n = 0 to 3 Figure C-12 Port C Block Diagram...
Page 397: Appendix D Port States In The Different Processing States
Appendix D Port States in the Different Processing States Table D-1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active to P1 High Retained Retained High Retained Functions Functions impedance impedance* to P2 High Retained Retained High Retained Functions Functions impedance...
Page 398: Appendix E Product Code Lineup
Appendix E Product Code Lineup Table E-1 H8/3814U Series Product Code Lineup Package (Hitachi Product Product Order Code Package Type Code Mark Code Name Code) H8/3814U Mask ROM Standard HD6433814UH HD6433814U(***)H HD6433814U(***)H 100-pin QFP version products (FP-100B) HD6433814UF HD6433814U(***)F HD6433814U(***)F 100-pin QFP...
Page 399: Appendix F Package Dimensions
Appendix F Package Dimensions Dimensional drawings of H8/3814U Series packages FP-100B and FP-100A are shown in figures F-1 and F-2 below. unit: mm 16.0 ± 0.3 0.5 mm Pitch 0.20 ± 0.10 0.08 M 0 – 10 ° 0.50 ± 0.20 0.10...
Page 400 Hitachi code FP-100A JEDEC code – EIAJ code SC-580-J Weight (g) – Figure F-2 FP-100A Package Dimensions Note: In case of inconsistencies arising within figures, dimensional drawings listed in the Hitachi Semiconductor Packages Manual take precedence and are considered correct.
Page 401 H8/3814U Series Hardware Manual Publication Date: 1st Edition, September 1995 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Document Center Hitachi Microcomputer System Ltd. Copyright © Hitachi, Ltd., 1995. All rights reserved. Printed in Japan.

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