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Fujitsu MB90335 Series Hardware Manual

16-bit microcontroller
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  • Page 1 The following document contains information on Cypress products.
  • Page 2 FUJITSU MICROELECTRONICS CM44-10137-6E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90335 Series HARDWARE MANUAL...
  • Page 4 MC-16LX 16-BIT MICROCONTROLLER MB90335 Series HARDWARE MANUAL For the information for microcontroller supports, see the following web site. "Customer Design Review Supplement" This web site includes the which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development.
  • Page 6 This manual contains the following 23 chapters and appendix. Chapter 1 OVERVIEW This chapter describes basics to give the understanding of the MB90335 Series as a whole such as the features, block diagrams, and overviews of the functions. Chapter 2 CPU This chapter explains the setting and operation of the CPU.
  • Page 7 Chapter 8 I/O PORT This chapter describes the overview of the I/O port and the register configuration/function used in the I/O port. Chapter 9 TIME-BASE TIMER This chapter describes the overview of the time-base time, register configuration/function, interrupt, and operation of the time-base timer. Chapter 10 WATCHDOG TIMER This chapter describes the overview of the watchdog timer, register configuration/function, and operation of the watchdog timer.
  • Page 8 Chapter 22 DUAL OPERATION FLASH MEMORY This chapter describes the function and operation of the dual operation flash memory. Chapter 23 EXAMPLE of CONNECTING SERIAL WRITING This chapter describes examples of serial write connection when using AF220/AF210/AF120/AF110 flash microcontroller programmer made by Yokogawa Digital Computer Corporation. APPENDIX Appendix includes detailed information on I/O map, interrupt vector, and instruction list, which are not mentioned in this manual and information that is needed for programming.
  • Page 9 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third- party's intellectual property right or other right by using such information.
  • Page 10: Table Of Contents

    CONTENTS CHAPTER 1 OVERVIEW ....................1 Feature of MB90335 Series ........................ 2 Block Diagram ............................ 7 Package Dimension ..........................8 Pin Assignment ........................... 9 Pin Function ............................10 I/O Circuit Types ..........................13 Handling of Device ..........................16 CHAPTER 2 CPU ......................
  • Page 11 3.6.4 Procedure for Use of Extended Intelligent I/O Service (EI OS) ..........80 3.6.5 Extended Intelligent I/O Service (EI OS) Processing Time ............81 Exception Processing Interrupt ......................84 Interruption by μDMAC ........................85 μDMAC Function ......................... 86 3.8.1 Register of μDMAC ........................87 3.8.2 3.8.3 DMA Descriptor Window Register (DDWR) .................
  • Page 12 CHAPTER 8 I/O PORT ....................163 Functions of I/O Ports ........................164 I/O Port Register ..........................165 8.2.1 Port Data Register (PDR0 to PDR2, PDR4 to PDR6) ............... 166 8.2.2 Port Direction Register (DDR0 to DDR2, DDR4 to DDR6) ............167 8.2.3 Other Registers .........................
  • Page 13 CHAPTER 12 USB HOST ....................243 12.1 Feature of USB HOST ........................244 12.2 Restriction on USB HOST ......................245 12.3 Block Diagram of USB HOST ......................246 12.4 Register of USB HOST ........................247 12.4.1 Host Control Register 0,1(HCNT0/HCNT1) ................250 12.4.2 Host Interruption Register (HIRQ) .....................
  • Page 14 14.1.2 Block Diagram of 16-bit Reload Timer ..................321 14.2 Registers of 16-bit Reload Timer ....................322 14.2.1 Timer Control Status Register 0 (TMCSR0) ................323 14.2.2 16-bit Timer Register 0 (TMR0)/16-bit Reload Register 0 (TMRLR0) ........327 14.3 Movement of 16-bit Reload Timer ....................329 14.3.1 State Transition of Counter Operation ..................
  • Page 15 18.4.4 Serial Input Data Register 0, 1 (SIDR0, SIDR1) and Serial Output Data Register 0, 1 (SODR0, SODR1) ........................400 18.4.5 UART Prescaler Control Register 0, 1 (UTCR0, UTCR1) and UART Prescaler Reload Register 0, 1 (UTRLR0, UTRLR1) ........................402 18.5 UART Interrupt ..........................
  • Page 16 CHAPTER 22 DUAL OPERATION FLASH MEMORY ........... 475 22.1 Overview of Dual Operation Flash Memory ..................476 22.2 Sector/Bank Configuration of Flash Memory .................. 478 22.3 Registers of Flash Memory ......................480 22.3.1 Flash Memory Control Status Register (FMCS) ................ 481 22.3.2 Flash Memory Write Control Register (FWR0/FWR1) ...............
  • Page 18 Main changes in this edition Page Changes (For details, refer to main body.) − − USB Mini-HOST → USB HOST CHAPTER 1 OVERVIEW Changed Package 1.3 Package Dimension FPT-64P-M09 → FPT-64P-M23 ■ Package Dimension (LQFP-64) CHAPTER 1 OVERVIEW Changed Package 1.3 Pin Assignment FPT-64P-M09 →...
  • Page 19 Page Changes (For details, refer to main body.) CHAPTER 22 DUAL OPERATION Changed figure. FLASH MEMORY Corrected flowchart. 22.7.4 Erasing Any Data in Flash Memory (Sector Erasing) Figure 22.7-2 APPENDIX B Instructions Changed Figure B.3-5. B.3 Direct Addressing (MOVW A, i : 0C0H → MOVW A, I:0C0H) ●...
  • Page 20 Page Changes (For details, refer to main body.) APPENDIX B Instructions Changed Table B.9-5. · Moved "MUL A" and "MULW A" instruction from column:60 to B.9 Instruction Map column:70. · Changed mnemonic and moved the Instruction from column:60, row:+A to column:70, row:+A. (DIVU →...
  • Page 22: Chapter 1 Overview

    CHAPTER 1 OVERVIEW This chapter describes basics to give the understanding of the MB90335 series as a whole such as the features, block diagrams, and overviews of the functions. 1.1 Feature of MB90335 Series 1.2 Block Diagram 1.3 Package Dimension 1.4 Pin Assignment...
  • Page 23: Feature Of Mb90335 Series

    1.1 Feature of MB90335 Series MB90335 Series Feature of MB90335 Series The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB function enables not only 12-Mbps Function operations but also simplified Host operations.
  • Page 24 CHAPTER 1 OVERVIEW 1.1 Feature of MB90335 Series MB90335 Series ● Capacity of built-in ROM and ROM type • Mask ROM: 64 Kbytes • Flash ROM: 64 Kbytes ● Built-in RAM • Mass production products: 4 Kbytes • Flash products: 4 Kbytes •...
  • Page 25 CHAPTER 1 OVERVIEW 1.1 Feature of MB90335 Series MB90335 Series ● • USB function (Correspond to USB Full Speed): 1 channel • USB HOST: 1 channel FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 26 CHAPTER 1 OVERVIEW 1.1 Feature of MB90335 Series MB90335 Series ■ Product Lineup Table 1.1-1 MB90335 Series Product Lineup List (1 / 2) Product name MB90V330A * MB90F337 MB90337 Classification Evaluation product Flash memory product Mask ROM product ROM Size...
  • Page 27 CHAPTER 1 OVERVIEW 1.1 Feature of MB90335 Series MB90335 Series Table 1.1-1 MB90335 Series Product Lineup List (2 / 2) Product name MB90V330A * MB90F337 MB90337 It is (multi/no multi External bus interface None correspondence). The others 9 I/O pins with 5 V tolerant (including pins also used for I...
  • Page 28: Block Diagram

    CHAPTER 1 OVERVIEW 1.2 Block Diagram MB90335 Series Block Diagram Figure 1.2-1 shows the block diagram of a MB90335 series. ■ Block Diagram of the MB90335 Series Figure 1.2-1 Block Diagram of the MB90335 Series X0,X1 Clock control circuit MC-16LX core...
  • Page 29: Package Dimension

    CHAPTER 1 OVERVIEW 1.3 Package Dimension MB90335 Series Package Dimension MB90335 series is available in one type of package. ■ Package Dimension (LQFP-64) Figure 1.3-1 Package Dimension of LQFP-64 Type 64-pin plastic LQFP Lead pitch 0.65 mm Package width ×...
  • Page 30: 1.4 Pin Assignment

    CHAPTER 1 OVERVIEW 1.4 Pin Assignment MB90335 Series 1.4 Pin Assignment Figure 1.4-1 shows the pin assignments of a MB90335 series. ■ Pin Assignment (FPT-64P-M23) Figure 1.4-1 Pin Assignments of the MB90335 Series (FPT-64P-M23) UTEST P24/PPG0 MB90335 Series TOP VIEW...
  • Page 31: Pin Function

    CHAPTER 1 OVERVIEW 1.5 Pin Function MB90335 Series Pin Function Table 1.5-1 describes the MB90335 series pin functions. ■ Pin Function Table 1.5-1 Pin Function (1 / 3) Circuit Pin No. Pin Name Functional description Type It is oscillation pin.
  • Page 32 CHAPTER 1 OVERVIEW 1.5 Pin Function MB90335 Series Table 1.5-1 Pin Function (2 / 3) Circuit Pin No. Pin Name Functional description Type It is General-purpose I/O port. SOT1 Functions as a data output pin for UART ch.1. It is General-purpose I/O port.
  • Page 33 CHAPTER 1 OVERVIEW 1.5 Pin Function MB90335 Series Table 1.5-1 Pin Function (3 / 3) Circuit Pin No. Pin Name Functional description Type It is General-purpose I/O port (Withstand voltage of 5 V). INT7 Function as input pins for external interrupt ch.7.
  • Page 34: I/O Circuit Types

    CHAPTER 1 OVERVIEW 1.6 I/O Circuit Types MB90335 Series I/O Circuit Types Table 1.6-1 shows I/O circuit types for pins of a MB90335 series. ■ I/O Circuit Types Table 1.6-1 I/O Circuit Types (1 / 3) Classification Circuit Remarks • Oscillation return resistance: X1, X0 about 1 MΩ...
  • Page 35 CHAPTER 1 OVERVIEW 1.6 I/O Circuit Types MB90335 Series Table 1.6-1 I/O Circuit Types (2 / 3) Classification Circuit Remarks • CMOS hysteresis input with pull-up • Resistance: About 50 kΩ CMOS hysteresis input • CMOS hysteresis input with pull-down •...
  • Page 36 CHAPTER 1 OVERVIEW 1.6 I/O Circuit Types MB90335 Series Table 1.6-1 I/O Circuit Types (3 / 3) Classification Circuit Remarks USB I/O pins D + Input D - Input Differential input Full D + Output Full D - Output Low D + Output...
  • Page 37: Handling Of Device

    CHAPTER 1 OVERVIEW 1.7 Handling of Device MB90335 Series Handling of Device This section describes the precautions when handling devices. ■ Precautions when Handling Devices ● Preventing Latch-up, Turning on Power Supply Latch-up may occur on CMOS IC under the following conditions: •...
  • Page 38 On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu Microelectronics will not guarantee results of operations if such failure occurs.
  • Page 39 CHAPTER 1 OVERVIEW 1.7 Handling of Device MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 40: Chapter 2 Cpu

    2.1 Overview of the CPU 2.2 Memory Space 2.3 Linear Addressing 2.4 Bank Addressing 2.5 Multibyte Data in Memory Space 2.6 Registers 2.7 Register Bank 2.8 Prefix Codes 2.9 Interrupt Disable Instructions Code: CM44-00101-2E Page: 20, 20 CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 41: Overview Of The Cpu

    CHAPTER 2 CPU 2.1 Overview of the CPU MB90335 Series Overview of the CPU The F MC-16LX CPU core is a 16-bit CPU designed for applications that require high- speed real-time processing, such as consumer or vehicle-mounted equipments. The MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.
  • Page 42: Memory Space

    CHAPTER 2 CPU 2.2 Memory Space MB90335 Series Memory Space MC-16LX CPU has the memory space of 16Mbytes. ■ Overview of CPU Memory Space An F MC-16LX CPU has 16Mbytes of memory space where all data program I/Os managed by the F 16LX CPU are located.
  • Page 43 CHAPTER 2 CPU 2.2 Memory Space MB90335 Series ■ ROM Area ● Vector table area (address: FFFC00 to FFFFFF • This area is used as a vector table for the reset, interrupt, and CALLV vectors. • This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address.
  • Page 44 CHAPTER 2 CPU 2.2 Memory Space MB90335 Series ■ Address Generation Methods The F MC-16LX has the following two addressing methods: ● Linear addressing An 24-bit address is specified by an instruction. ● Bank addressing Upper 8-bit of an address are specified by an appropriate bank register, and the remaining lower 16-bit of an address are specified by an instruction.
  • Page 45: Linear Addressing

    CHAPTER 2 CPU 2.3 Linear Addressing MB90335 Series Linear Addressing There are two types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Uses the lower 24-bit of a 32-bit general-purpose register contents as the address.
  • Page 46: Bank Addressing

    CHAPTER 2 CPU 2.4 Bank Addressing MB90335 Series Bank Addressing In the bank method, the 16 M byte space is divided into 256 of 64 K byte banks. The following five bank registers are used to specify the banks corresponding to each space: •...
  • Page 47 CHAPTER 2 CPU 2.4 Bank Addressing MB90335 Series Table 2.4-1 Default Space Default space Addressing Program space PC indirect, program access, branch Data space @A, addr16, dir, and addressing using @RW0, @RW1, @RW4, or @RW5 Stack space Addressing using PUSHW, POPW, @RW3, or @RW7...
  • Page 48: Multibyte Data In Memory Space

    CHAPTER 2 CPU 2.5 Multibyte Data in Memory Space MB90335 Series Multibyte Data in Memory Space Multibyte data is allocated from the low-order addresses to the high-order addresses in the memory space in the order from the byte in LSB to the byte in MSB.
  • Page 49: Registers

    CHAPTER 2 CPU 2.6 Registers MB90335 Series Registers The F MC-16LX registers are largely classified into two types: dedicated registers and general-purpose registers. The dedicated registers exist as dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture.
  • Page 50 CHAPTER 2 CPU 2.6 Registers MB90335 Series Figure 2.6-1 Dedicated Resisters Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program counter bank register Data bank register User bank register System stack bank register Additional data bank register...
  • Page 51 CHAPTER 2 CPU 2.6 Registers MB90335 Series ■ General-purpose Registers As described in Figure 2.6-2, the F MC-16LX general-purpose registers are located from 000180 00037F (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses is currently being used as a register bank. Each bank has the following three types of registers.
  • Page 52: Accumulator (A)

    CHAPTER 2 CPU 2.6 Registers MB90335 Series 2.6.1 Accumulator (A) The accumulator (A) register consists of 2 × 16-bit arithmetic operation registers (AH and AL), and is used as a temporary register for operation results and transfer data. ■ Accumulator (A) During 32-bit data processing, AH and AL are used together (see Figure 2.6-3).
  • Page 53: User Stack Pointer (Usp) And System Stack Pointer (Ssp)

    CHAPTER 2 CPU 2.6 Registers MB90335 Series 2.6.2 User Stack Pointer (USP) and System Stack Pointer (SSP) User stack pointer (USP) and system stack pointer (SSP) are 16-bit registers that indicate the memory addresses for saving/restoring data when a push/pop instruction or subroutine is executed.
  • Page 54: Processor Status (Ps)

    CHAPTER 2 CPU 2.6 Registers MB90335 Series 2.6.3 Processor Status (PS) The processor status (PS) register consists of the bits controlling the CPU operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.6-6, the upper bytes of the PS register consist of the register bank pointers (RP) and the interrupt level mask register (ILM) that indicate the starting address of a register bank.
  • Page 55 CHAPTER 2 CPU 2.6 Registers MB90335 Series ● Zero flag (Z) The Z flag is set to "1" when the operation result is all "0". Otherwise, Z flag is cleared to "0". ● Overflow flag (V) The V flag is set when an overflow of a signed value occurs as a result of operation execution. In other cases, V flag is cleared to "0".
  • Page 56 CHAPTER 2 CPU 2.6 Registers MB90335 Series Table 2.6-1 Levels Indicated by the Interrupt Level Mask Register (ILM) ILM2 ILM1 ILM0 Level value Acceptable interrupt level Interrupts disabled Level value less than 1 (0 only) Level value less than 2 (0 and 1)
  • Page 57: Program Counter (Pc)

    CHAPTER 2 CPU 2.6 Registers MB90335 Series 2.6.4 Program Counter (PC) Program counter (PC) shows lower 16-bit of the memory address of the instruction code that CPU should execute. ■ Program Counter (PC) The program counter (PC) register is a 16-bit counter that indicates the lower 16 bits of the memory address of an instruction code to be executed by the CPU.
  • Page 58: Bank Registers (Pcb, Dtb, Usb, Ssb, Adb)

    CHAPTER 2 CPU 2.6 Registers MB90335 Series 2.6.5 Bank Registers (PCB, DTB, USB, SSB, ADB) The bank register shows the memory bank where the program space, the data space, the user stack space, the system stack space, and the Additional space are arranged.
  • Page 59: Direct Page Register (Dpr)

    CHAPTER 2 CPU 2.6 Registers MB90335 Series 2.6.6 Direct Page Register (DPR) This section explains the direct page register (DPR) functions. ■ Direct Page Register (DPR) <Initial Value: 01 > The direct page register (DPR) specifies, as shown in Figure 2.6-11, addresses 8 to 15 of an instruction operand in the direct addressing mode.
  • Page 60: Register Bank

    CHAPTER 2 CPU 2.7 Register Bank MB90335 Series Register Bank A register bank that consists of 8 words can be used as the general-purpose registers for the arithmetic operations or as the pointers for the instructions, such as byte registers (R0 to R7), word registers (RW0 to RW7), and long word registers (RL0 to RL3).
  • Page 61: Prefix Codes

    CHAPTER 2 CPU 2.8 Prefix Codes MB90335 Series Prefix Codes Placing a prefix code before an instruction can partially change the operation of the instruction. 3 types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix.
  • Page 62 CHAPTER 2 CPU 2.8 Prefix Codes MB90335 Series ● POPW PS Either SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction. ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction.
  • Page 63 CHAPTER 2 CPU 2.8 Prefix Codes MB90335 Series ● JCTX @A CCR changes according to the instruction specifications regardless of the prefix. ● MOV ILM,imm8 The instruction is executed normally, but the prefix affects the next instruction. FUJITSU MICROELECTRONICS LIMITED...
  • Page 64: Interrupt Disable Instructions

    CHAPTER 2 CPU 2.9 Interrupt Disable Instructions MB90335 Series Interrupt Disable Instructions Interrupt requests are not accepted about following 10 instructions: MOV ILM, #imm8 OR CCR, #imm8 AND CCR, #imm8 POPW PS ■ Interrupt Disable Instructions As shown in Figure 2.9-1, if a valid hardware interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed.
  • Page 65 CHAPTER 2 CPU 2.9 Interrupt Disable Instructions MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 66: Chapter 3 Interrupt

    INTERRUPT This chapter describes the interruption, extended intelligent I/O service (EI OS), and direct memory access controller (μDMAC) of MB90335 Series. 3.1 Outline of Interrupt 3.2 Interrupt Cause and Interrupt Vector 3.3 Interrupt Control Register and Peripheral Function 3.4 Hardware Interrupt 3.5 Software Interrupt...
  • Page 67: Outline Of Interrupt

    CHAPTER 3 INTERRUPT 3.1 Outline of Interrupt MB90335 Series Outline of Interrupt MC-16LX has the following five interrupt functions, which suspend the current process when an event occurs and transfer control to a separately defined program. • Hardware Interrupt • Software interrupt •...
  • Page 68 CHAPTER 3 INTERRUPT 3.1 Outline of Interrupt MB90335 Series ● Software interrupt Transfers control to the user-defined interrupt handing program by executing the instruction dedicated to software interrupt (for example, INT instruction). Figure 3.1-2 Overview of Software Interrupts Register file...
  • Page 69 CHAPTER 3 INTERRUPT 3.1 Outline of Interrupt MB90335 Series ● Interruption by μDMAC μDMAC is involved in automatic data transfer between peripheral functions and memory. EI OS performs data transfer by DMA transfer although it was previously performed by the interrupt handling program.
  • Page 70: Interrupt Cause And Interrupt Vector

    CHAPTER 3 INTERRUPT 3.2 Interrupt Cause and Interrupt Vector MB90335 Series Interrupt Cause and Interrupt Vector MC-16LX has functions that are associated with 256 types of interrupt causes, and 256 interrupt vector tables are assigned to the most significant address area of memory.
  • Page 71 CHAPTER 3 INTERRUPT 3.2 Interrupt Cause and Interrupt Vector MB90335 Series ■ Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers Table 3.2-2 shows the relationship between the causes of interrupts except software interrupt, and the interrupt vectors and control registers.
  • Page 72 CHAPTER 3 INTERRUPT 3.2 Interrupt Cause and Interrupt Vector MB90335 Series : Available. With EI OS stop function. (The interrupt request flag is cleared by the interrupt clear signal. With a stop request.) ❍ : Available. (The interrupt request flag is cleared by the interrupt clear signal.) Δ...
  • Page 73: Interrupt Control Register And Peripheral Function

    CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90335 Series Interrupt Control Register and Peripheral Function Interrupt control registers (ICR00 to ICR15) located in the interrupt controller, are associated with all the peripheral functions which have the interrupt function. This register controls the interrupt and the extended intelligent I/O service (EI OS).
  • Page 74 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90335 Series ■ Interrupt Control Register Functions Each of the interrupt control register (ICR) has the following four functions. • Setting of interrupt level for peripheral function • Selection of whether to perform normal interrupt or external intelligent for corresponding peripheral function (EI •...
  • Page 75: Interrupt Control Registers (Icr00 To Icr15)

    CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90335 Series 3.3.1 Interrupt Control Registers (ICR00 to ICR15) Interrupt control registers (ICR00 to ICR15) associated with all the peripheral functions provided with the interrupt function, controls the handling which takes place when an interrupt request is generated.
  • Page 76 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90335 Series Figure 3.3-2 Interrupt Control Register (ICR00 to ICR15) at Read At read Address Initial value 0000B0 - - 000111 0000BF Interrupt level set bit Interrupt level 0 (Highest)
  • Page 77: Interrupt Control Register Functions

    CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90335 Series 3.3.2 Interrupt Control Register Functions Each of the interrupt control register (ICR00 to ICR15) consists of the following bits, which have four functions. • Interrupt level set bits (IL2 to IL0) •...
  • Page 78 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90335 Series ■ Interrupt Control Register Functions ● Interrupt level set bits (IL2 to IL0) Specifies the interrupt level for the associated peripheral function. Initialized to level 7 (no interrupts) by reset.
  • Page 79 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90335 Series Table 3.3-3 Correspondence between EI OS Channel Select Bits and Descriptor Addresses ICS3 ICS2 ICS1 ICS0 Channel to be selected Descriptor address 000100 000108 000110 000118 000120 000128...
  • Page 80: Hardware Interrupt

    CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series Hardware Interrupt Hardware interrupt suspends the active program execution by the CPU in response to an interrupt request signal generated by a peripheral function, resulting in transfer of control to the user-defined interrupt handling program. Extended intelligent I/O service OS), μDMAC, external interrupts, and other similar processes are also executed as a...
  • Page 81 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series ■ Construction of Hardware Interrupt As shown in Table 3.4-1, there are four features related to hardware interrupt. These four must be programmed when hardware interrupt is used. Table 3.4-1 Mechanism Related to Hardware Interrupt...
  • Page 82 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series ● Hardware interrupt suppression of interrupt suppression instruction Table 3.4-2 shows the hardware interrupt suppression instruction. If a hardware interrupt request is generated during execution of the hardware interrupt suppression instruction, an interrupt is processed after execution of the hardware interrupt suppression instruction and then other instruction.
  • Page 83: Operation Of Hardware Interrupt

    CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series 3.4.1 Operation of Hardware Interrupt The following describes the operation sequence from generation of a hardware interrupt request to completion of interrupt handling. ■ Start of Hardware Interrupt ● Operation of peripheral function (generation of interrupt request) Any peripheral function provided with the hardware interrupt request function has "interrupt request flag"...
  • Page 84 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series ■ Operation of Hardware Interrupt Figure 3.4-2 shows the operation sequence from generation of a hardware interrupt to completion of interrupt handling. Figure 3.4-2 Operation of Hardware Interrupt Internal bus PS, PC...
  • Page 85: Operation Flow Of Hardware Interrupt

    CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series 3.4.2 Operation Flow of Hardware Interrupt When the peripheral function generates an interrupt request, the interrupt controller notifies the CPU of the interrupt level. If the CPU is ready to accept the interrupt, it suspends the currently active instruction;...
  • Page 86: Procedure For Using A Hardware Interrupt

    CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series 3.4.3 Procedure for Using a Hardware Interrupt Use of hardware interrupt requires the system stack area, peripheral functions, and interrupt control registers (ICR) to be set up. ■ Procedure for Using a Hardware Interrupt Figure 3.4-4 shows an example of the procedure for using a hardware interrupt.
  • Page 87: Multiple Interrupts

    CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series 3.4.4 Multiple Interrupts Multiple hardware interrupts can be implemented. To do so, set different interrupt levels for interrupt level set bits (IL0 to IL2) of the ICR in response to two or more interrupt OS and multiple μDMAC...
  • Page 88 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series ■ Example of Multiple Interrupts Aa an example of multiple interrupt processing, set the 8/16-bit PPG timer interrupt level to 2 and the timer interrupt level to "1", considering a case when timer interrupts are to be given higher priority than 8/16-bit PPG timer interrupts.
  • Page 89: Hardware Interrupt Processing Time

    CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series 3.4.5 Hardware Interrupt Processing Time Before the interrupt handling routine can be executed after a hardware interrupt request is generated, the time to complete of the currently active instruction and the interrupt handling time are required.
  • Page 90 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90335 Series The interrupt handling time depends on the address to which the stack pointer points. Table 3.4-3 shows the compensation values (Z) of the interrupt handling time. One machine cycle is equal to one clock cycle of the machine clock (φ).
  • Page 91: Software Interrupt

    CHAPTER 3 INTERRUPT 3.5 Software Interrupt MB90335 Series Software Interrupt The software interrupt function transfers control from the currently active program by the CPU to the user-defined interrupt handling program in response to execution of the software interrupt instruction (INT instruction).
  • Page 92 CHAPTER 3 INTERRUPT 3.5 Software Interrupt MB90335 Series ■ Operation of Software Interrupt Figure 3.5-1 shows the operation sequence from generation of a software interrupt to completion of interrupt handling. Figure 3.5-1 Operation of Software Interrupt Internal bus PS, PC...
  • Page 93: Interrupts By Extended Intelligent I/O Service (Ei 2 Os)

    CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series Interrupts by Extended Intelligent I/O Service (EI The extended intelligent I/O service (EI OS) executes automatic data transfer between the peripheral function (I/O) and memory. A hardware interrupt is generated at the end of the data transfer.
  • Page 94 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series ■ Operation of Extended Intelligent I/O Service (EI Figure 3.6-1 shows the operation of the EI Figure 3.6-1 Operation of Extended Intelligent I/O Service (EI Memory space...
  • Page 95: Extended Intelligent I/O Service (Ei 2 Os) Descriptor (Isd)

    CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series 3.6.1 Extended Intelligent I/O Service (EI OS) Descriptor (ISD) Extended intelligent I/O service (EI OS) descriptor (ISD) is existed to the addresses 000100 to 00017F in the internal RAM and consists of 8 bytes x 16 channels.
  • Page 96 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series Table 3.6-1 Correspondence between Channel Numbers and Descriptor Addresses Channel Descriptor address 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170...
  • Page 97: Os) Descriptor (Isd)

    CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series 3.6.2 Each Register of Extended Intelligent I/O Service (EI Descriptor (ISD) The extended intelligent I/O service (EI OS) descriptor (ISD) consists of the following registers. • Data counter (DCT) •...
  • Page 98 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series ■ Extended Intelligent I/O Service (EI OS) Status Register (ISCS) The extended intelligent I/O service status register (ISCS) updates or fixes the buffer address and I/O register address pointers by the 8-bit length register. It also indicates the transfer data format (byte or word) and the direction of transfer.
  • Page 99 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series ■ Buffer Address Pointer (BAP) The buffer address pointer (BAP), a 24-bit register, contains the address used for the next attempt of transfer by EI OS. The BAP is provided independently for the EI OS channels to enable the EI channels to transfer data between any address of 16 Mbytes and I/O.
  • Page 100: Operation Of Extended Intelligent I/O Service (Ei 2 Os)

    CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series 3.6.3 Operation of Extended Intelligent I/O Service (EI If the peripheral function has generated an interrupt request and activation of EI OS has been set in the associated interrupt control register (ICR), the CPU will execute data transfer using EI OS.
  • Page 101: Procedure For Use Of Extended Intelligent I/O Service (Ei 2 Os)

    CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series 3.6.4 Procedure for Use of Extended Intelligent I/O Service (EI To use extended intelligent I/O service (EI OS), the system stack area, EI OS descriptor, peripheral function, interrupt control register (ICR), and other requirements must be set ■...
  • Page 102: Extended Intelligent I/O Service (Ei 2 Os) Processing Time

    CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series 3.6.5 Extended Intelligent I/O Service (EI OS) Processing Time The time required for extended intelligent I/O service (EI OS) processing depends on the following factors: • Setting of EI OS status register (ISCS) •...
  • Page 103 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series Further, correction may be required, depending on the condition for executing EI OS, as shown in Table 3.6-3. Table 3.6-3 Compensation Value for Data Transfer at EI...
  • Page 104 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI MB90335 Series ● At the end caused by an end request from the peripheral function (I/O) If data transfer by EI OS is aborted due to an end request from the peripheral function (I/O) (ICR:S1, S0= 11), the hardware interrupt is activated without performing data transfer.
  • Page 105: Exception Processing Interrupt

    CHAPTER 3 INTERRUPT 3.7 Exception Processing Interrupt MB90335 Series Exception Processing Interrupt MC-16LX executes exception handling by executing undefined instructions. Exception handling, basically the same as interrupt, is executed when an exception item is detected during a period between instructions, the normal process is suspended for this purpose.
  • Page 106: Interruption By Μdmac

    CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series Interruption by μDMAC μDMAC is a simplified DMA with the same function as EI 3.8.1 μDMAC Function 3.8.2 Register of μDMAC 3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) 3.8.2.2 DMA Status Register (DSRH/DSRL) 3.8.2.3 DMA Stop Status Register (DSSR)
  • Page 107: Μdmac Function

    CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series μDMAC Function 3.8.1 μDMAC is simple DMA with the function equal with EI ■ μDMAC Function μDMAC has the following functions. • Performs automatic data transfer between the peripheral resource (I/O) and memory.
  • Page 108: Register Of Μdmac

    CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series Register of μDMAC 3.8.2 μDMAC has four registers: DCSR, DSR, DSSR, and DER. The DMA descriptor used to set up DMA transfer is described in "3.8.3 DMA Descriptor Window Register (DDWR)".
  • Page 109 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) DMA descriptor channel specification register (DCSR) switches the descriptor of each channel. The descriptor is set after the channel is specified by this register.
  • Page 110 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series [bit11 to bit8] DCSRx: Specifies the DMA descriptor channel. Table 3.8-1 Relation between DCSR and Selector Channel DCSR3 to DCSR0 Selection channel Resource interrupt request 0000 USB function 1 (End Point 0-IN)
  • Page 111 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.2.2 DMA Status Register (DSRH/DSRL) DMA status register (DSRH/DSRL) indicates that the DMA transfer ended. When "1" is set to this register, the interrupt is generated at the same time. ■ Bit Configuration of DMA Status Register (DSRH/DSRL) Figure 3.8-3 Bit Configuration of DMA Status Register (DSRH/DSRL)
  • Page 112 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.2.3 DMA Stop Status Register (DSSR) DMA stop status register (DSSR) indicates that the DMA transfer stopped due to the STOP request. The meaning of the bit in this register is different depending on the STP bit of the DMA descriptor channel specification register (DCSR).
  • Page 113 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series Notes: • DSSR is controlled by most significant bit (STP) of DCSR. If STP is "0", STP8 to STP15 will be selected as being used for the DSSR. If it is "1", STP0 to STP7 will be used for the DSSR.
  • Page 114 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.2.4 DMA Enable Register (DERH/DERL) DMA enable register (DERH/DERL) enables the DMA transfer. When "1" is set to this register, the interrupt request, which is the DMA transfer request, generates to the corresponding channel, and starts the DMA transfer.
  • Page 115: Dma Descriptor Window Register (Ddwr)

    CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.3 DMA Descriptor Window Register (DDWR) The DMA descriptor, consisting of 8 bytes × 16 channels, is used to set up DMA transfer. One of the 16 channels is specified, and mapped to the DMA descriptor window register (DDWR) for being accessible.
  • Page 116 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.3.1 DMA Data Counter (DDCTH/DDCTL) DMA data counter (DDCTH/DDCTL) sets the data transfer. When DDCTH/DDCTL is "0000 ", the DMA transfer ends. ■ DMA Data Counter (DDCTH/DDCTL) DMA data counter (DDCTH/DDCTL), a 16-bit length register, indicates the counter associated with transferred number.
  • Page 117 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.3.2 DMA I/O Register Address Pointer (DIOAH/DIOAL) DMA I/O register address pointer (DIOAH/DIOAL) sets the I/O address pointer. The upper address (A23 to A16) is fixed at "00 ". ■ DMA I/O Register Address Pointer (DIOAH/DIOAL) The DMA I/O register address pointer (DIOAH/DIOAL), a 16-bit length register, indicates the 16 low order bits (A15 to A00) of the DMA I/O register address.
  • Page 118 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.3.3 DMA Control Register (DMACS) DMA control register (DMACS) controls the DMA transfer. The following can be controlled by the DMACS. → → • Direction control (IOA BAP and BAP IOA) •...
  • Page 119 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series Figure 3.8-10 Wait Specification Bit Explanation source destination wait source destination Length of wait part in transfer such as above figure is defined by RDY2 and RDY1. Note: If writing transmission data to UART by using μDMAC, not setting RDY2 and RDY1 bit of DMACS register in (0, 0).
  • Page 120 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series 3.8.3.4 DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) DMA buffer address pointer (DBAPH/DBAPM/DBAPL) sets the buffer address pointer. The DBAPH/DBAPM/DBAPL can be set A23 to A00. ■ DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) The DMA buffer address pointer (DBAPH/DBAPM/DBAPL), a 24-bit register, contains the address used for DMA transfer.
  • Page 121: Explanation Of Operation Of Μdmac

    CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series Explanation of Operation of μDMAC 3.8.4 This section describes the μDMAC operation. ■ Operation of μDMAC Figure 3.8-12 shows the Operation of μDMAC. Data transfer using μDMAC performs the following steps in order: 1.
  • Page 122 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90335 Series ■ μDMAC Use Procedure Figure 3.8-13 shows the procedure for using μDMAC. Figure 3.8-13 Use Procedure of μDMAC Software processing Hardware processing (Interrupt generation) START ENx=1 of appropriate ch Setting System stack area...
  • Page 123: Exceptions

    Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu Microelectronics recommends using exception processing only for debugging or for activating emergency recovery software.
  • Page 124: Stack Operation Of Interrupt Processing

    CHAPTER 3 INTERRUPT 3.10 Stack Operation of Interrupt Processing MB90335 Series 3.10 Stack Operation of Interrupt Processing Once an interrupt is accepted, the contents of the dedicated registers are automatically saved in the system stack before control branches to the interrupt handling. Return from the stack at the end of the interrupt handling also takes place automatically.
  • Page 125 CHAPTER 3 INTERRUPT 3.10 Stack Operation of Interrupt Processing MB90335 Series ■ Stack Area ● Securing stack area The stack area is used to save or return the program counter (PC) used to execute the subroutine call (CALL) or vector call (CALLV) instruction as well as execute the interrupt handling. This area is also used, by the PUSHW or POPW instruction, to save or return the contents of temporary registers and their related data.
  • Page 126: Program Example Of Interrupt Processing

    CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing MB90335 Series 3.11 Program Example of Interrupt Processing An example of interrupt processing program is shown below. ■ Program Example of Interrupt Processing ● Processing specification An example interruption program that uses external interruption 0 (INT0) ●...
  • Page 127 CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing MB90335 Series LOOP ; Unconditional jump ;----------Interrupt Program------------------------------------------------------------ ED_INT1: I:EIRR, #00H ; New acceptance of INT0 prohibited RETI ; Returns from interrupt. CODE ENDS ;----------Vector Settings------------------------------------------------------------------ VECT CSEG ABS=0FFH 0FFB4H ; The vector is set in interruption #18(12...
  • Page 128 CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing MB90335 Series ● Coding example DDR6 000016H ; Port 6 direction register ENIR 00003CH ; Interruption/DTP permission register EIRR 00003DH ; Interruption/DTP factor register ELVR 00003EH ; A register to specify the required level...
  • Page 129 CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing MB90335 Series DCTL,#64H ; Sets transfer byte count (100 bytes) DCTH,#00H I:ICR00,#00001000B ; EI OS ch.0, EI OS enable, interrupt level 0 (highest) I:ELVR,#00000001B ; Make INT0 "H" level request I:EIRR,#00H ;...
  • Page 130: Delayed Interrupt Generation Module

    CHAPTER 3 INTERRUPT 3.12 Delayed Interrupt Generation Module MB90335 Series 3.12 Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate a task switching interrupt. Use of this module enables F MC-16LX CPU to generate or cancel an interrupt request.
  • Page 131: Operation Of Delayed Interrupt Generation Module

    CHAPTER 3 INTERRUPT 3.12 Delayed Interrupt Generation Module MB90335 Series 3.12.1 Operation of Delayed Interrupt Generation Module When the CPU writes "1" to the appropriate bit of the DIRR by software, the request latch in the delay interrupt generation module is set, resulting in generation of the interrupt request to the interrupt controller.
  • Page 132: Chapter 4 Reset

    CHAPTER 4 RESET This chapter explains reset of the MB90335 series. 4.1 Outline of Reset 4.2 Reset Factors and Oscillation Stabilization Wait Times 4.3 External Reset Pin 4.4 Reset Operation 4.5 Reset Factor Bit 4.6 State of Each Pin at Reset...
  • Page 133: Outline Of Reset

    CHAPTER 4 RESET 4.1 Outline of Reset MB90335 Series Outline of Reset When the reset cause is generated, the CPU suspends the currently executed process immediately before entering the wait state for release of the reset. After the reset is cleared, processing starts from the address indicated in the reset vector.
  • Page 134 CHAPTER 4 RESET 4.1 Outline of Reset MB90335 Series ● External reset An external reset is generated by inputting the "L" level signal to external reset pin (RST). The input time of the "L" level signal to the (RST) pin must be continued for 16 machine cycles (16/φ) or more.
  • Page 135: Reset Factors And Oscillation Stabilization Wait Times

    4.2 Reset Factors and Oscillation Stabilization Wait Times MB90335 Series Reset Factors and Oscillation Stabilization Wait Times There are four kinds of reset factors of MB90335 series. The oscillation stabilization wait time varies with the reset cause. ■ Reset Factors and Oscillation Stabilization Wait Times Table 4.2-1 shows the relationship between the reset causes and the oscillation stabilization wait time.
  • Page 136 CHAPTER 4 RESET 4.2 Reset Factors and Oscillation Stabilization Wait Times MB90335 Series Figure 4.2-1 Oscillation Stabilization Wait Times for the Evaluation/flash and MASK Products during Power on Reset Time Evaluation/Flash Products /HCLK /HCLK operation Down-conversion Oscillation Stabilizing Stabilizing Wait Time...
  • Page 137: External Reset Pin

    The external reset pin (RST pin), dedicated to reset input pin, generates an internal reset in response to input of the "L" level signal. MB90335 series are reset in sync with the CPU operating clock, except for external pin in asynchronous (generated through ports and so on), which change to the reset state.
  • Page 138: Reset Operation

    CHAPTER 4 RESET 4.4 Reset Operation MB90335 Series Reset Operation Once the reset is released, the object from which to read the mode data and reset vector is selected by setting the mode pin, before the mode fetch is performed. This fetch determines the CPU operation mode and the execution activation address succeeding the reset operation.
  • Page 139 CHAPTER 4 RESET 4.4 Reset Operation MB90335 Series ■ Mode Fetch Once the reset is released, the CPU transfers the reset vector and mode data into the appropriate register in the CPU core. The reset vector and mode data are assigned to the four bytes of FFFFDC...
  • Page 140: Reset Factor Bit

    CHAPTER 4 RESET 4.5 Reset Factor Bit MB90335 Series Reset Factor Bit A reset factor can be identified by reading the watchdog timer control register (WDTC). ■ Reset Factor Bit There are the flip-flop registers associated with respective reset causes, as shown in Figure 4.5-1. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC).
  • Page 141 CHAPTER 4 RESET 4.5 Reset Factor Bit MB90335 Series ■ Correspondence of Reset Factor Bit and Reset Factor Figure 4.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Contents of reset cause bits and associated reset causes are shown in the Table 4.5-1.
  • Page 142: State Of Each Pin At Reset

    CHAPTER 4 RESET 4.6 State of Each Pin at Reset MB90335 Series State of Each Pin at Reset This section explains the state of each pin at reset. ■ Pin Status during Reset The state of each pin during reset is determined by the settings of the mode pins (MD2 to MD0).
  • Page 143 CHAPTER 4 RESET 4.6 State of Each Pin at Reset MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 144: Chapter 5 Clock

    CHAPTER 5 CLOCK This chapter explains the clock of the MB90335 series. 5.1 Outline of Clock 5.2 Block Diagram of Clock Generation Section 5.3 Clock Select Register (CKSCR) 5.4 Clock Mode 5.5 Oscillation Stabilization Wait Time 5.6 Connection of Oscillator and External Clock...
  • Page 145: Outline Of Clock

    CHAPTER 5 CLOCK 5.1 Outline of Clock MB90335 Series Outline of Clock The clock generation section controls operation of the internal clock which is the operation clock for the CPU and peripheral functions. The following are four kinds of the clock.
  • Page 146 CHAPTER 5 CLOCK 5.1 Outline of Clock MB90335 Series ■ Clock Supply Map Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and peripheral function. For this reason, operation of the peripheral functions is influenced by switching clock mode between the main and PLL clock or switching the PLL clock frequency multiplication rate.
  • Page 147: Block Diagram Of Clock Generation Section

    CHAPTER 5 CLOCK 5.2 Block Diagram of Clock Generation Section MB90335 Series Block Diagram of Clock Generation Section The clock generation section consists of the following five blocks: • System clock generation circuit • PLL multiplying circuit • Clock selector •...
  • Page 148 CHAPTER 5 CLOCK 5.2 Block Diagram of Clock Generation Section MB90335 Series ● System clock generation circuit Generates an oscillation clock (HCLK) using the oscillator connected to the high-speed oscillation pin. It is also possible to input an external clock.
  • Page 149: Clock Select Register (Ckscr)

    CHAPTER 5 CLOCK 5.3 Clock Select Register (CKSCR) MB90335 Series Clock Select Register (CKSCR) The clock select register (CKSCR) switches the clock mode between the main, sub, and PLL clocks, and selects the oscillation stabilization wait time and the PLL clock frequency multiplier.
  • Page 150 CHAPTER 5 CLOCK 5.3 Clock Select Register (CKSCR) MB90335 Series Note: The machine clock selection bit (MCS) is initialized by reset to main clock selection. Table 5.3-1 Functions of Clock Select Register (CKSCR) Bits Bit name Functions Reserved: bit15 The bit always returns "1" when read.
  • Page 151: Clock Mode

    CHAPTER 5 CLOCK 5.4 Clock Mode MB90335 Series Clock Mode The clock modes are the main clock mode and PLL clock mode. ■ Main Clock Mode, PLL Clock Mode ● Main clock mode The main clock mode stops the PLL clock by using an oscillation clock frequency divided by 2 as the operating clock of the CPU and peripheral resources.
  • Page 152 CHAPTER 5 CLOCK 5.4 Clock Mode MB90335 Series ■ Machine Clock The PLL clock and main clock output from the PLL multiplying circuit are used as machine clocks. These machine are clocks supplied to the CPU or peripheral function. One of the main and PLL modes can be selected by writing the CKSCR of MCS bit.
  • Page 153: Oscillation Stabilization Wait Time

    CHAPTER 5 CLOCK 5.5 Oscillation Stabilization Wait Time MB90335 Series Oscillation Stabilization Wait Time When power is turned on, the stop mode is quit, the oscillation stabilization wait time is required after the oscillation begins. This is because the oscillation of the oscillation clock remains in stopped state.
  • Page 154: Connection Of Oscillator And External Clock

    5.6 Connection of Oscillator and External Clock MB90335 Series Connection of Oscillator and External Clock MB90335 series, containing a system clock generator circuit, generates the clock with the oscillator connected externally. It is also possible to input an externally generated clock.
  • Page 155 CHAPTER 5 CLOCK 5.6 Connection of Oscillator and External Clock MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 156: Chapter 6 Low-Power Consumption Mode

    CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter describes the low-power consumption mode of the MB90335 series. 6.1 Outline of Low-Power Consumption Mode 6.2 Block Diagram of Low-power Consumption Control Circuit 6.3 Low-power Consumption Mode Control Register (LPMCR) 6.4 CPU Intermittent Operation Mode 6.5 Standby Mode...
  • Page 157: Outline Of Low-Power Consumption Mode

    6.1 Outline of Low-Power Consumption Mode MB90335 Series Outline of Low-Power Consumption Mode The MB90335 series have the following CPU operation modes by selecting the operation clock and operating the control of the clock. • Clock mode (PLL clock mode and main clock mode) •...
  • Page 158 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Outline of Low-Power Consumption Mode MB90335 Series ■ Clock Mode ● PLL clock mode In PLL clock mode, the CPU and peripheral function operate on a PLL multiplying clock of oscillation clock (HCLK). Note: When using USB HOST and the USB function, you need to set to the PLL clock mode.
  • Page 159 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Outline of Low-Power Consumption Mode MB90335 Series ● Stop mode Stop mode is mode for stopping original oscillation and all functions are stopped. Note: In the stop mode, data is kept at the lowest power consumption since the oscillation clock is terminated.
  • Page 160: Block Diagram Of Low-Power Consumption Control Circuit

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.2 Block Diagram of Low-power Consumption Control Circuit MB90335 Series Block Diagram of Low-power Consumption Control Circuit The low-power consumption control circuit is composed of the following seven blocks. • CPU intermittent operation selector • Standby controller circuit •...
  • Page 161 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.2 Block Diagram of Low-power Consumption Control Circuit MB90335 Series ● CPU intermittent operation selector The CPU intermittent operation sector selects the number of the suspended clocks in the CPU intermittent operation mode. ● Standby controller circuit The standby controller circuit controls the CPU clock control circuit and the peripheral clock control circuit, and then performs the transition to the low-power consumption mode or cancellation.
  • Page 162: Low-Power Consumption Mode Control Register (Lpmcr)

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90335 Series Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) performs transition to/ cancellation of the low-power consumption mode or sets the number of the CPU clock suspend cycles in the CPU intermittent operation mode.
  • Page 163 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90335 Series Table 6.3-1 Function Description of Each Bit of Low-power Consumption Mode Control Register (LPMCR) Bit name Functions • This bit indicates the transition to the stop mode.
  • Page 164 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90335 Series ■ Access to Low-power Consumption Mode Control Register Transition to the low-power consumption modes (stop mode, sleep mode, and time-base timer mode) by writing to the low-power consumption mode control register is made, in this case, be sure to use the instructions in Table 6.3-2.
  • Page 165: Cpu Intermittent Operation Mode

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.4 CPU Intermittent Operation Mode MB90335 Series CPU Intermittent Operation Mode The CPU intermittent operation mode is a mode for reducing the power consumption by intermittently operating the CPU while operating the external bus and peripheral functions at high speed.
  • Page 166: Standby Mode

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90335 Series Standby Mode Standby modes are: sleep (PLL sleep, main sleep), time-base timer, and stop mode. ■ Operation Status in Standby Mode Table 6.5-1 shows the operation state in the standby mode.
  • Page 167: Sleep Mode

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90335 Series 6.5.1 Sleep Mode Sleep mode is mode for stopping the CPU operation clock and the operation other than CPU continues. When you instruct the transition to the sleep mode with the low-power...
  • Page 168 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90335 Series ■ Cancellation of Sleep Modes The low-power consumption control circuit clears sleep mode by reset input or interrupt generation. ● Return by reset Initialization to the main clock mode is made by reset.
  • Page 169: Time-Base Timer Mode

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90335 Series 6.5.2 Time-base Timer Mode The time-base timer mode terminates the original oscillation and all the operations other than the time-base timer and the watch timer, resulting in termination of all the functions other than the time-base timer and the watch timer.
  • Page 170: Stop Mode

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90335 Series 6.5.3 Stop Mode Stop mode is mode for stopping original oscillation and all functions are stopped. That means, data can be held with the lowest power consumption. ■ Transition to Stop Mode If you write "1"...
  • Page 171 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90335 Series Notes: • When handling an interrupt, the CPU usually services the interrupt after executing the instruction that follows the one specifying the stop mode. • In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the CPU returns from PLL stop mode, therefore, it is necessary to allow for the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time.
  • Page 172: State Transition Diagram

    The transition of the operation state and the transition conditions of MB90335 series are shown. ■ State Transition Diagram Figure 6.6-1 shows the transition of the operation state and the transition conditions of MB90335 series. Figure 6.6-1 State Transition and Transition Conditions External reset, Watchdog timer reset, Software reset...
  • Page 173 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.6 State Transition Diagram MB90335 Series ■ Operation Status in Low-power Consumption Mode Table 6.6-1 lists the operation states in low-power consumption mode. Table 6.6-1 Operation States in Low-power Consumption Mode Main Time-base Clock Operating State...
  • Page 174: State Of The Pin During Standby Mode, And Reset

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, and Reset MB90335 Series State of the Pin during Standby Mode, and Reset The state of the pin at the time of the stand by mode, or the reset is shown for each memory access code.
  • Page 175: Precautions When Using Low-Power Consumption Mode

    CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Precautions when Using Low-power Consumption Mode MB90335 Series Precautions when Using Low-power Consumption Mode Special attention for the following is needed when using the low-power consumption mode. • Transition to standby mode and interrupt •...
  • Page 176 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Precautions when Using Low-power Consumption Mode MB90335 Series ■ Oscillation Stabilization Wait Time ● Oscillation Stabilization Wait Time of oscillation clock Because the oscillator for original oscillation is stopped in stop mode, the oscillation stabilization wait time must be required.
  • Page 177 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Precautions when Using Low-power Consumption Mode MB90335 Series ■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode ● To access the low-power consumption mode control register (LPMCR) with assembler language •...
  • Page 178: Chapter 7 Mode Setting

    CHAPTER 7 MODE SETTING This chapter describes the mode setting and the external memory access. 7.1 Mode Setting 7.2 Mode Pins (MD2 to MD0) 7.3 Mode Data CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 179: Mode Setting

    CHAPTER 7 MODE SETTING 7.1 Mode Setting MB90335 Series Mode Setting MC-16LX has respective modes in the access method, access area, and test. Respective mode is set according to the mode pin at the time of reset and the mode- fetched mode data.
  • Page 180: Mode Pins (Md2 To Md0)

    Internal Mode Data sequence is controlled with mode data Setting disabled Flash serial writing Flash writer write mode Note: MB90335 series can be used on the single chip mode only. Therefore, please set MD2:0=V MD1, MD0:1=V CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 181: Mode Data

    Table 7.3-1 Content of M1 and M0 Bit Setting Function Single-chip mode (Setting prohibited) (Setting prohibited) (Setting prohibited) Note: MB90335 series can be used on the single chip mode only. Please set M1, M0 = 00 FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 182 Table 7.3-2 shows the relation between the mode pin and the mode data. Table 7.3-2 Relation between Mode Pin and Mode Data Mode Single Chip Note: MB90335 series can be used on the single chip mode only. CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 183 CHAPTER 7 MODE SETTING 7.3 Mode Data MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 184: Chapter 8 I/O Port

    CHAPTER 8 I/O PORT This chapter describes the configuration and functions of the register used in the I/O port. 8.1 Functions of I/O Ports 8.2 I/O Port Register CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 185: Functions Of I/O Ports

    I/O pin in bit unit by the port direction register (DDR). The MB90335 Series has 37 input/output pins and 8 open drain output pins. P07 to P00, P17 to P10, P27 to P20,P47 to P40, and P54 to P50 are I/O ports. P67 to P60 are N-ch open drain pins.
  • Page 186: I/O Port Register

    CHAPTER 8 I/O PORT 8.2 I/O Port Register MB90335 Series I/O Port Register The configuration and functions of the register used in the I/O port are described. ■ I/O Port Registers There are the following registers in I/O port. • Port data register (PDR0 to PDR2, PDR4 to PDR6) •...
  • Page 187: Port Data Register (Pdr0 To Pdr2, Pdr4 To Pdr6)

    CHAPTER 8 I/O PORT 8.2 I/O Port Register MB90335 Series 8.2.1 Port Data Register (PDR0 to PDR2, PDR4 to PDR6) The configuration and functions of the port data register (PDR0 to PDRB) are described. ■ Port Data Register (PDR0 to PDR2, PDR4 to PDR6) Figure 8.2-1 shows the list of the port data register (PDR0 to PDR2, PDR4 to PDR6).
  • Page 188: Port Direction Register (Ddr0 To Ddr2, Ddr4 To Ddr6)

    CHAPTER 8 I/O PORT 8.2 I/O Port Register MB90335 Series 8.2.2 Port Direction Register (DDR0 to DDR2, DDR4 to DDR6) The configuration and functions of the port direction register are described. ■ Port Direction Register (DDR0 to DDR2, DDR4 to DDR6) Figure 8.2-2 shows the list of the port direction register (DDR0 to DDR2, DDR4 to DDR6).
  • Page 189: Other Registers

    CHAPTER 8 I/O PORT 8.2 I/O Port Register MB90335 Series 8.2.3 Other Registers The configuration and functions of the register other than the port data register (PDR0 to PDR2, PDR4 to PDR6) and the port direction register (DDR0 to DDR2, DDR4 to DDR6) are described.
  • Page 190: Chapter 9 Time-Base Timer

    9.1 Overview of Time-base Timer 9.2 Configuration of Time-base Timer 9.3 Time-base Timer Control Register (TBTC) 9.4 Interrupt of Time-base Timer 9.5 Operations of Time-base Timer 9.6 Precautions when Using Time-base Timer 9.7 Program Example of Time-base Timer CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 191: Overview Of Time-Base Timer

    CHAPTER 9 TIME-BASE TIMER 9.1 Overview of Time-base Timer MB90335 Series Overview of Time-base Timer The time-base timer has a interval timer function that enables a selection of four interval times using 18-bit free-run counter (time-base counter) count-up with synchronizing to the internal count clock (2 division of original oscillation).
  • Page 192 CHAPTER 9 TIME-BASE TIMER 9.1 Overview of Time-base Timer MB90335 Series ■ Function of Clock Supply The clock supply function supplies the operating clock to the timer for oscillation stabilization wait time and some peripheral functions. Table 9.1-2 shows the clock cycle supplied from the time-base timer to each peripheral.
  • Page 193: Configuration Of Time-Base Timer

    CHAPTER 9 TIME-BASE TIMER 9.2 Configuration of Time-base Timer MB90335 Series Configuration of Time-base Timer The time-base timer consists of the following four blocks. • Time-base timer counter • Counter clear circuit • Interval timer selector • Time-base timer control register (TBTC) ■...
  • Page 194 CHAPTER 9 TIME-BASE TIMER 9.2 Configuration of Time-base Timer MB90335 Series ● Time-base timer counter This is an 18-bit up-counter whose count clock is two-division clock of oscillation clock (HCLK). ● Counter clear circuit This circuit clears the counter by writing "0" to time-base timer initialization bit (TBR) of time-base timer control register (TBTC), power-on reset, transition to the stop mode, switching to PLL clock mode from the main clock mode.
  • Page 195: Time-Base Timer Control Register (Tbtc)

    CHAPTER 9 TIME-BASE TIMER 9.3 Time-base Timer Control Register (TBTC) MB90335 Series Time-base Timer Control Register (TBTC) The time-base timer control register (TBTC) executes interval time selection, time-base timer counter clearance, and interrupt control and status check. ■ Time-base Timer Control Register (TBTC) Figure 9.3-1 Time-base Timer Control Register (TBTC)
  • Page 196 CHAPTER 9 TIME-BASE TIMER 9.3 Time-base Timer Control Register (TBTC) MB90335 Series Table 9.3-1 Time-base Timer Control Register (TBTC) Bit name Functions Reserved: Note: bit15 Reserved bit Be sure to write "1". • The value at the time of reading is irregular.
  • Page 197: Interrupt Of Time-Base Timer

    CHAPTER 9 TIME-BASE TIMER 9.4 Interrupt of Time-base Timer MB90335 Series Interrupt of Time-base Timer The time-base timer can generate an interrupt request by the overflow of the specified bit of the time-base timer counter (interval timer function). ■ Interrupt of Time-base Timer...
  • Page 198: Operations Of Time-Base Timer

    CHAPTER 9 TIME-BASE TIMER 9.5 Operations of Time-base Timer MB90335 Series Operations of Time-base Timer The time-base timer has functions of interval timer and clock supply to peripheral functions. ■ Operation of Interval Timer Function (Time-base Timer) Interval timer function generates interrupt requests at regular intervals. In order to function as an interval timer, setup in Figure 9.5-1 is needed.
  • Page 199 CHAPTER 9 TIME-BASE TIMER 9.5 Operations of Time-base Timer MB90335 Series Table 9.5-1 Time-base Timer Counter Clearance Operation and Oscillation Stabilization Wait Time Counter Operation TBOF Oscillation Stabilization Wait Time Clear Writing "0" to time-base timer ❍ ❍ initialization bit (TBR) of time-base timer...
  • Page 200: Precautions When Using Time-Base Timer

    CHAPTER 9 TIME-BASE TIMER 9.6 Precautions when Using Time-base Timer MB90335 Series Precautions when Using Time-base Timer Cautions about influences on peripheral functions due to interrupt request and time- base timer clearances. ■ Precautions when Using Time-base Timer ● Clearing Interrupt request...
  • Page 201 CHAPTER 9 TIME-BASE TIMER 9.6 Precautions when Using Time-base Timer MB90335 Series ■ Operations of Time-base Timer Operations in the following situations are shown in Figure 9.6-1. • At a power-on reset occurs. • At a transition to sleep mode during the operation of interval timer function •...
  • Page 202: Program Example Of Time-Base Timer

    CHAPTER 9 TIME-BASE TIMER 9.7 Program Example of Time-base Timer MB90335 Series Program Example of Time-base Timer Programming examples for the time-base timer are shown below. ■ Program Example of Time-base Timer ● Processing specification Interval interruptions of 2 /HCLK (oscillation clock) are repeatedly generated. In this case, the interval time is about 0.68 ms (at 6 MHz operation).
  • Page 203 CHAPTER 9 TIME-BASE TIMER 9.7 Program Example of Time-base Timer MB90335 Series 0FF6CH ; The interruption vector is set WARI 0FFDCH ; Reset vector setting START ; Single-chip mode VECT ENDS START FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 204: Chapter 10 Watchdog Timer

    This chapter describes the function and operation of the watchdog timer. 10.1 Overview of Watchdog Timer 10.2 Watchdog Timer Control Register (WDTC) 10.3 Configuration of Watchdog Timer 10.4 Operations of Watchdog Timer 10.5 Precautions when Using Watchdog Timer 10.6 Program Examples of Watchdog Timer CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 205: Overview Of Watchdog Timer

    CHAPTER 10 WATCHDOG TIMER 10.1 Overview of Watchdog Timer MB90335 Series 10.1 Overview of Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the time-base timer or clock timer as the count clock and resets the CPU when the counter is not cleared for a preset period of time.
  • Page 206: Watchdog Timer Control Register (Wdtc)

    CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) MB90335 Series 10.2 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) displays the activation, clearance, and reset factor of the watchdog timer. ■ Watchdog Timer Control Register (WDTC) Figure 10.2-1 shows the watchdog timer control register (WDTC).
  • Page 207 CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) MB90335 Series Table 10.2-1 Function of Each Bit of Watchdog Timer Control Register (WDTC) Bit name Functions • Read-only bits that indicate reset factors. When a reset factor occurs, the relevant bit is set to "1".
  • Page 208: Configuration Of Watchdog Timer

    CHAPTER 10 WATCHDOG TIMER 10.3 Configuration of Watchdog Timer MB90335 Series 10.3 Configuration of Watchdog Timer The watchdog timer consists of following five blocks. • Count clock selector • Watchdog counter (two bits counter) • Watchdog reset generator circuit • Counter clear control circuit •...
  • Page 209: Operations Of Watchdog Timer

    CHAPTER 10 WATCHDOG TIMER 10.4 Operations of Watchdog Timer MB90335 Series 10.4 Operations of Watchdog Timer The watchdog timer generates a watchdog reset upon an overflow of the watchdog counter. ■ Operations of Watchdog Timer Figure 10.4-1 shows the setting required to operate the watchdog timer.
  • Page 210 CHAPTER 10 WATCHDOG TIMER 10.4 Operations of Watchdog Timer MB90335 Series Figure 10.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer [Block diagram of Watchdog timer] 2-bit counter 2 divided 2 divided Reset Clock selector Reset circuit signal...
  • Page 211: Precautions When Using Watchdog Timer

    CHAPTER 10 WATCHDOG TIMER 10.5 Precautions when Using Watchdog Timer MB90335 Series 10.5 Precautions when Using Watchdog Timer This section explains precautions when using watchdog timer. ■ Precautions when Using Watchdog Timer ● Stopping watchdog timer Once the watchdog time is activated, it cannot stop until power-on or a watchdog-external reset occurs.
  • Page 212: Program Examples Of Watchdog Timer

    CHAPTER 10 WATCHDOG TIMER 10.6 Program Examples of Watchdog Timer MB90335 Series 10.6 Program Examples of Watchdog Timer Program example of watchdog timer is given below. ■ Program Examples of Watchdog Timer ● Processing specification • The watchdog timer is cleared each time in loop of the main program.
  • Page 213 CHAPTER 10 WATCHDOG TIMER 10.6 Program Examples of Watchdog Timer MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 214: Chapter 11 Usb Function

    This chapter describes the functions and overview of the USB Function. 11.1 Overview of USB Function 11.2 Block Diagram of USB Function 11.3 Registers of USB Function 11.4 Operation Explanation of USB Function Manual code: CM44-00104-1E CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 215: Overview Of Usb Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.1 Overview of USB Function 11.1 Overview of USB Function The USB Function is an interface that supports the USB (Universal Serial Bus) communication protocol. It operates supporting the transfer speed of FULL (12 Mbps) and has the following characteristics.
  • Page 216: Block Diagram Of Usb Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.2 Block Diagram of USB Function 11.2 Block Diagram of USB Function Figure 11.2-1 shows the USB Function block diagram. ■ Block Diagram of USB Function Figure 11.2-1 Block Diagram of USB Function EndPoint0...
  • Page 217: Registers Of Usb Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3 Registers of USB Function The configuration and functions of registers used in the USB Function are described. ■ Register List of USB Function Figure 11.3-1 Register List of USB Function...
  • Page 218 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function Figure 11.3-2 Registers of USB Function Address:0000D0 RESUM HCON USTP Reserved Reserved RFBK UDC control register (UDCC) Address:0000D1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Address:0000D2 Reserved PKS0...
  • Page 219 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function (Continued) Address:0000E6 SIZE EP1 status register (EP1S) Address:0000E7 BFINI DRQIE SPKIE Reserved BUSY SIZE Address:0000E8 Reserved SIZE EP2 status register (EP2S) Address:0000E9 BFINI DRQIE SPKIE Reserved BUSY Reserved Address:0000EA...
  • Page 220: Udc Control Register (Udcc)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.1 UDC Control Register (UDCC) UDC control register (UDCC) controls the UDC core circuit. ■ UDC Control Register (UDCC) Figure 11.3-3 shows the bit configuration of the UDC control register (UDCC).
  • Page 221 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function Note: The RST bit initializes the corresponding bits of the timestamp register, UDC status register, and interrupt enable register at once. In addition, since it sets EP0I, EP0O, and BFINIs of EP1 to EP5 status registers at the same time after initialization, clear the RST bit (which does not clear the BFINI bits), and clear the BFINI of an endpoint to be used in this sequence.
  • Page 222 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function Note: If the USTP bit is not used in the stop mode, wait for 3 cycles or 43 cycles to elapse in FULL speed or in LOW speed (that is supported only in HOST mode) so that you can ensure that the reset operation will function when you have set RST=1.
  • Page 223: Ep0 Control Register (Ep0C)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.2 EP0 Control Register (EP0C) EP0 control register (EP0C) controls concerning end point 0. ■ EP0 Control Register (EP0C) Figure 11.3-4 shows the bit configuration of the EP0 control register (EP0C).
  • Page 224 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function Note: The STALL response is continued to the host while the STAL bit is set. The USB Function returns from STALL status when it receives a normal SETUP packet after the STAL bit is deselected.
  • Page 225: Ep1 To Ep5 Control Register (Ep1C To Ep5C)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.3 EP1 to EP5 Control Register (EP1C to EP5C) EP1 to EP5 control register (EP1C to EP5C) controls concerning end point 1 to end point 5. ■ EP1 to EP5 Control Register (EP1C to EP5C) Figure 11.3-5 shows the bit configuration of the EP1 to EP5 control register (EP1C to EP5C).
  • Page 226 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function EPEN Operating mode End Point is invalid. End Point is assumed to be effective. [bit14, bit13] TYPE: End point forwarding type selection bits The forwarding type supported by the end point is specified.
  • Page 227 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit10] NULE: NULL automatic transfer enable bit This bit sets up a mode where the last packet transfer will be detected and 0-byte data transfer will be automatically sent when IN- direction data transfer request arrives if the automatic buffer transfer mode is set (DMAE=1).
  • Page 228 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function Note: Setting any number not less than a maximum number of transfer (100 or 40 ) and "00 " are prohibited. Please write "00" in bit8, bit7 about EndPoint2 to EndPoint5. In addition, when using the automatic buffer transfer mode (DMAE=1), setting bit0 to bit2 in the corresponding EndPoint is forbidden.
  • Page 229: Time Stamp Register (Tmsp)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.4 Time Stamp Register (TMSP) The time stamp register (TMSP) displays a frame number when an SOF packet is received. ■ Time Stamp Register (TMSP) Figure 11.3-6 shows the bit configuration of the timestamp register (TMSP).
  • Page 230: Udc Status Register (Udcs)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.5 UDC Status Register (UDCS) The UDC status register (UDCS) is a register that indicates the status of a bus on USB communications and a particular command received. Each bit in the register except SETP indicates an interrupt factor and raises an interrupt to CPU if its corresponding interrupt enable bit is specified and valid.
  • Page 231 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit3] BRST: Bus reset detection bit The detection of USB bus reset is displayed. The BRST bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write.
  • Page 232 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit0] CONF: Configuration detection bit It displays the fact that the USB Function has been configured. The CONF bit is set when a SetConfig, a USB command, has been successfully received. The CONF bit is an interrupt factor and writing "1" is ignored.
  • Page 233: Udc Interruption Enable Register (Udcie)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.6 UDC Interruption Enable Register (UDCIE) The UDC interrupt enable register (UDCIE) is a register that allows each interrupt factor in the UDC status register to be raised as an interrupt bit wisely except CONFN.
  • Page 234 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit11] BRSTIE: Bus reset interruption permission bit It allows an interrupt due to the interrupt factor for the UDC status register "BRST" to be generated. BRSTIE Operating mode Interrupt disabled by BRST factor...
  • Page 235: Ep0I Status Register (Ep0Is)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.7 EP0I Status Register (EP0IS) The EP0I status register (EP0IS) displays status related to transfer toward In for EndPoint0. ■ EP0I Status Register (EP0IS) Figure 11.3-9 shows the bit configuration of the EP0I Status Register (EP0IS).
  • Page 236 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit14] DRQIIE: Transmit data interrupt enable bits It allows an interrupt due to the interrupt factor for the EP0I status register "DRQI" to be generated. DRQIIE Operating mode Interrupt disabled by DRQI factor...
  • Page 237: Ep0O Status Register (Ep0Os)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.8 EP0O Status Register (EP0OS) The EP0O status register (EP0OS) displays status related to transfer toward out for EndPoint0. ■ EP0O Status Register (EP0OS) Figure 11.3-10 shows the bit configuration of the EP0O Status Register (EP0OS).
  • Page 238 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit14] DRQOIE: Received data interruption permission bit It allows an interrupt due to the interrupt factor for the EP0O status register "DRQO" to be generated. DRQOIE Operating mode Interrupt disabled by DRQO factor...
  • Page 239 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit8, bit7] Reserved bits These bits are reserved bits. Writing has no effect on the operation. Reading is undefined. [bit6 to bit0] SIZE: Packet size display bit When OUT packets have been transferred from EP0, the number of data bytes that has been written into the receive buffer is displayed.
  • Page 240: Ep1 To Ep5 Status Register (Ep1S To Ep5S)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.9 EP1 to EP5 Status Register (EP1S to EP5S) The EP1 to EP5 status registers (EP1S to EP5S) displays status related to EndPoint1 to EndPoint5. ■ EP1 to EP5 Status Register (EP1S to EP5S) Figure 11.3-11 shows the bit configurations of the EP1 to EP5 status registers (EP1S to EP5S).
  • Page 241 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit15] BFINI: Transmission/receive buffer initialization bit The transmission and reception buffer of the forwarding data is initialized. The BFINI bit is automatically set by setting the RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit.
  • Page 242 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit11] BUSY: Busy flag bit It indicates that writing into the transmission/receive buffer or accessing it for read from the HOST is under way. The BUSY bit is set by the automatic operation, and reset.
  • Page 243 CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function [bit9] SPK: Short packet interrupt request bit It indicates that the number of pieces of transfer data that has been successfully received from the host is less than a maximum number of packets set the PKS in the EP1 to EP5 control register (EP1C to EP5C) (including 0 packet).
  • Page 244: Ep0 To Ep5 Data Register (Ep0Dt To Ep5Dt)

    CHAPTER 11 USB FUNCTION MB90335 Series 11.3 Registers of USB Function 11.3.10 EP0 to EP5 Data Register (EP0DT to EP5DT) The EP0 to EP5 data registers (EP0DT to EP5DT) are access registers used to read or write into the transmission/receive buffer for transfer data related to EndPoint0 to EndPoint5.
  • Page 245: Operation Explanation Of Usb Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4 Operation Explanation of USB Function The USB Function conforms to the USB (Universal Serial Bus) communication protocol and supports basic protocol operations (handshake) by hardware. Consequently, only processing communication data can provide the USB communication.
  • Page 246 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function Figure 11.4-1 Connection Example of USB Cable Pin Direction Overview of operation USB bus connection Host Device Operation is not started until the host detects detection pull-up on the USB bus.
  • Page 247 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function ● Getting descriptor The device receives a request from the host PC and sends data to the host. In more detail, communications are performed in the following three stages: Figure 11.4-2 Communication Stage...
  • Page 248: Detecting Connection And Disconnection

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4.1 Detecting Connection and Disconnection This section describes how to detect connection to and disconnection from the USB host. ■ Example USB System Connection Connection to and disconnection from the USB host can be detected by connecting an external interrupt pin to the VBUS pin on the USB connector and connecting a pull-down resistor.
  • Page 249 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 3. Temporarily disable the external interrupt. Change the interrupt setting to detect "L" level inputs to the external interrupt pin, and then clear and re-enable the external interrupt.
  • Page 250: Each Register Operation When Command Responds

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4.2 Each Register Operation when Command Responds This section describes basic operations and control of registers and then how to process USB packets (architecture). Firmware tasks triggered via CPU interrupt are processed for each handshake operation.
  • Page 251 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function ● Command completion processing The DRQI is set when the status stage toward OUT has been completed. It enters a CPU interrupt process when the DRQO is set, confirms that the number of received data is 0, and clears the interrupt cause DRQO and returns to the interrupted point to prepare for the next setup stage.
  • Page 252: Stall Response And Release

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4.3 STALL Response and Release For Endpoint0 and For Endpoints 1 to 5, this section explains STALL response and release procedures. ■ STALL response and release procedures for Endpoint0 STALL response and release procedures for Endpoint0 are executed with STAL bit of EP0 Control Register (EP0C).
  • Page 253 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function • STAL Bit Clear Timing For STALL release, clears STAL bit at detecting SETP bit of "1" (DRQO bit = 1 for interrupt) that indicates the set-up stage of control transfer, and sets STAL bit if the STALL response is required. (See Figure 11.4-9.)
  • Page 254 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function Figure 11.4-10 Case where STALL response is executed with software processing Host or hub Function EPn (End Point n) Software of Function Macro Internal STAL bit Condition bit...
  • Page 255 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function • To automatically execute STALL response with hardware. The procedures to execute STAL response with hardware are shown in Figure 11.4-11. When STALL response is set with Set Feature command, the hardware would automatically set the internal condition bit of the relevant endpoint and gives the STALL response regardless of the STAL bit.
  • Page 256: Suspend Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4.4 Suspend Function A USB device must have a configuration of bus power supply where power consumption is 500μA or less in suspend status. The section covers a USB device from its transmitting to suspend status to its entering STOP mode.
  • Page 257: Wake-Up Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4.5 Wake-up Function To shift a USB device from suspend status to wake-up status, the USB protocol provides the following two ways: • Remote wake-up from device • Wake-up from host PC The above is explained.
  • Page 258: Dma Transfer Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4.6 DMA Transfer Function It is possible to transfer data between transmission/receive buffer and internal RAM that the USB Function communicates. You can select the following two modes in DMA...
  • Page 259 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function ● IN direction (host PC → device) forwarding Figure 11.4-16 IN Packet Forwarding IN packet IN packet Host PC Device DRQ flag * Device DRQ flag * DATA0...
  • Page 260 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function ■ Data Number Automatic Transfer Mode It sets the total number of pieces of data to be transferred in DMA and sets the transfer enable bit in advance. When DMAE is enabled and the DRQ is set after transfer from the HOST has been completed,...
  • Page 261 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function Figure 11.4-18 IN Direction (Device → Host PC) Forwarding Last data Data Host PC Device DRQ flag * DRQ flag * Device DATA1 DATA0 Automatic Automatic Host PC...
  • Page 262: Null Transfer Function

    CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function 11.4.7 NULL Transfer Function If data sent from the USB Function is the last packet and a maximum number of packets, it is possible to automatically transfer 0-byte data in the next packet transfer.
  • Page 263 CHAPTER 11 USB FUNCTION MB90335 Series 11.4 Operation Explanation of USB Function FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 264: Chapter 12 Usb Host

    12.1 Feature of USB HOST 12.2 Restriction on USB HOST 12.3 Block Diagram of USB HOST 12.4 Register of USB HOST 12.5 Operation of USB HOST 12.6 Each Token Flow Chart of USB HOST Manual code: CM44-00102-1E CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 265: Feature Of Usb Host

    CHAPTER 12 USB HOST 12.1 Feature of USB HOST MB90335 Series 12.1 Feature of USB HOST USB HOST provides minimum host operations required and is a function that enables data to be transferred to and from Device without PC intervention.
  • Page 266: Restriction On Usb Host

    CHAPTER 12 USB HOST 12.2 Restriction on USB HOST MB90335 Series 12.2 Restriction on USB HOST This section indicates Restriction on USB HOST. ■ Restriction on USB HOST HOST Support Hub ❍ ❍ Transfer Bulk transfer ❍ Control transfer ❍...
  • Page 267: Block Diagram Of Usb Host

    CHAPTER 12 USB HOST 12.3 Block Diagram of USB HOST MB90335 Series 12.3 Block Diagram of USB HOST Figure 12.3-1 shows the block diagram of USB HOST. ■ UART Block Diagram of USB HOST Figure 12.3-1 Block Diagram of USB HOST...
  • Page 268: Register Of Usb Host

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4 Register of USB HOST In USB HOST, there are the following ten types of registers: • Host control register 0,1(HCNT0/HCNT1) • Host interruption register (HIRQ) • Host error status register (HERR) •...
  • Page 269 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series (Continued) • Host state status register Address: 0000C4 Reserved ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT HSTATE → (R/W) (R/W) (R/W) (R/W) Read/Write → Initial value • SOF interruption FRAME comparison register...
  • Page 270 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series (Continued) • FRAME setting Register Address:0000CC FRAME0 HFRAME → (R/W) Read/Write → (00000000 Initial value Address:0000CD Reserved FRAME1 HFRAME → (R/W) Read/Write → (000 Initial value • Host token end point register...
  • Page 271: Host Control Register 0,1(Hcnt0/Hcnt1)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.1 Host Control Register 0,1(HCNT0/HCNT1) Host control registers 0,1(HCNT0/HCNT1) specify the USB operation mode and the settings of an interrupt. ■ Host Control Register 0, 1(HCNT0/HCNT1) Figure 12.4-1 Bit Configuration of Host Control Register 0, 1 (HCNT0/HCNT1)
  • Page 272 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 9] CANCEL: Token cancellation permission This bit sets whether a token is to be cancelled when the token (which is issued in an EOF area) has never been executed and is in waiting status if the SOFIRQ bit in the host interrupt register (HIRQ) is "1".
  • Page 273 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 5] CMPIRE: Completion interrupt request enable It sets whether an interrupt is generated when a token has been completed. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC).
  • Page 274 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 1] URST: USB bus reset It is set to USB bus whether reset is generated. It indicates "1" while the USB bus is being reset and turns "0" when it has been completed. It is forbidden to set it to "1" when the SUSP bit in the host state status register (HSTATE) is "1"...
  • Page 275: Host Interruption Register (Hirq)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.2 Host Interruption Register (HIRQ) The host interrupt register (HIRQ) indicates for the interrupt request flag for USB HOST. It can allow an interrupt to be generated by setting the interrupt enable bit in the host control registers (HCNT0/HCNT1) except the TCAN bit.
  • Page 276 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 4] URIRQ: USB bus interrupt request It is shown that reset in USB bus ended. When it becomes "1", it gets back to "0" by writing "0" to it.
  • Page 277 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 1] DIRQ: Cutting interrupt request It is shown to have detected cutting the device. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the DIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1".
  • Page 278: Host Error Status Register (Herr)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.3 Host Error Status Register (HERR) The host error status register (HERR) is a register that indicates whether an error occurs or not when sending or receiving data in host mode.
  • Page 279 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 13] TOUT: Time-out It indicates whether time-out was generated. If "1" is cleared, write "0" to this bit. The bit is updated after the RST bit of the UDC control register (UDCC) is set to "0".
  • Page 280 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 9, bit 8] HS: Handshake status It indicates the status of handshake operations between transmission and reception in host mode. It indicates NULL when handshake operation is not performed due to any reasons such as an error and the SOF token is completed.
  • Page 281: Host State Status Register (Hstate)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.4 Host State Status Register (HSTATE) The host state status register (HSTATE) is a register that indicates the status of the USB circuit such as connections to devices and transfer mode. Note that the CLKSEL bit is also enabled in the function mode.
  • Page 282 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 3] SOFBUSY:SOF timer operation It indicates whether the SOF timer is operating in host mode. Sending SOF stops when "0" is done in the writing. To update them, you must set the RST bit in the UDC control register (UDCC) to "0".
  • Page 283 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series [bit 0] CSTAT: Connected state It is whether the device is connected is shown. The pin for HOST becomes an object. It is not initialized with the RST bit in the UDC control register (UDCC).
  • Page 284: Sof Interruption Frame Comparison Register (Hfcomp)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.5 SOF Interruption FRAME Comparison Register (HFCOMP) The SOF interrupt FRAME comparison register (HFCOMP) is a register used to set data that is compared with the lower 8 bits of FRAME Number for SOF token. If the lower 8 bits of FRAME Number is compared with the HFCOMP register and a match is detected with the SOFIRE bit in host control register 0 (HCNT0) set to "1", an interrupt will be...
  • Page 285: Retry Timer Setting Register (Hrtimer)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.6 Retry Timer Setting Register (HRTIMER) The retry timer setting register (HRTIMER) is a register used to set a retry time period for a token. ■ Retry Timer Setting Register (HRTIMER) Figure 12.4-6 Bit Configuration of Retry Timer Setting Register (HRTIMER)
  • Page 286: Host Address Register (Hadr)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.7 Host Address Register (HADR) The host address register (HADR) is a register used for an address field when a token is sent. ■ Host Address Register (HADR) Figure 12.4-7 Bit Configuration of Host address Register (HADR)
  • Page 287: Eof Setting Register (Heof)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.8 EOF Setting Register (HEOF) The EOF setting register (HEOF) is a register that sets a time period for which a token is inhibited before the execution of the SOF token. If the data of the SOF timer turns out to...
  • Page 288: Frame Setting Register (Hframe)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.9 FRAME Setting Register (HFRAME) The FRAME setting register (HFRAME) is a register that sets a FRAME Number in handling SOF tokens. When you set the TKNEN bits of the host token endpoint register (HTOKEN) to SOF activation, the SOF timer starts and, afterwards, an SOF is automatically sent out every 1 ms.
  • Page 289: Host Token Endpoint Register (Htoken)

    CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series 12.4.10 Host Token Endpoint Register (HTOKEN) The host token endpoint register (HTOKEN) is a register that sets a toggle, endpoint, and token. ■ Host Token Endpoint Register (HTOKEN) Figure 12.4-10 Bit Configuration of Host Token Endpoint Register (HTOKEN)
  • Page 290 CHAPTER 12 USB HOST 12.4 Register of USB HOST MB90335 Series Table 12.4-3 Token Setting bit6 bit5 bit4 Operation No send out SETUP is sent IN is sent. OUT is sent. SOF is sent. Reserved (Set prohibition) Reserved (Set prohibition)
  • Page 291: Operation Of Usb Host

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5 Operation of USB HOST The operation of USB HOST is explained. ■ Operation of USB HOST ● Connection of device The software detects that the external USB device was connected.
  • Page 292: Connection Of Device

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.1 Connection of Device The method for detecting the connection of the external USB device by software is described. ■ Setting of HOST Function To make it operate as a host of the USB device, set the HOST bit of the host control register 0 (HCNT0) to "1".
  • Page 293 CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series Figure 12.5-1 Connecting Detection Timing Example of Speed Device (HCNT0 Bit 0 = 0) Device connection Pin D+ for HOST Pin D- for HOST 2.5μs CSTAT bit of HSTATE...
  • Page 294: Reset Of Usb Bus

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.2 Reset of USB Bus When you set the URST bit of the host control register 0 (HCNT0) to "1" in the host mode, it sends out SE0 for not less than 10 ms and resets the USB bus. When the USB bus has been reset, it sets back the URST bit of the host control register to "0"...
  • Page 295: Token Packet

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.3 Token Packet If you execute any of an IN token, OUT token, and SETUP token in the host mode, a token packet is started when you set necessary data in the host token register (HTOKEN) after you set the PKS bit of the EP1 control register (EP1C) or EP2 control register (EP2C) based on the host address register (HADR) and the DIR bit in EP1C.
  • Page 296 CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series incremented by 1. In this case, the CMPIRQ of the host interrupt register (HIRQ) is also set to "1", and the TKNEN bit of the host token endpoint register (HTOKEN) is cleared to 000 .
  • Page 297: Data Packet

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.4 Data Packet If a data packet is transmitted after a token packet has been sent, toggle data will be transmitted based on the TGGL bit of the host token endpoint register (HTOKEN), and the buffer data for endpoint 1 or endpoint 2 according to the DIR bit of the EP1 control register (EP1C), CRC16 data, and EOP is sent.
  • Page 298: Handshake Packet

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.5 Handshake Packet Transmission/reception partner must be informed of your own status via handshake packet. ■ Handshake Packet The reception side transmits one of ACK, NAK, and STALL when it determines through handshake packet whether it can receive data properly or the endpoint supports it.
  • Page 299: Retry Function

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.6 Retry Function At the termination of the packet, when NAK or an error such as CRC error occurs, and the RETRY bit of the host control register 1 (HCNT1) is "1", it continues to retry during a time period set in the retry timer register (HRTIMER).
  • Page 300: Sof Interrupt

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.7 SOF Interrupt Once you have set the SOFIRE bit of the host control register 0 (HCNT0) to "1", it sets the SOFIRQ bit of the host interrupt register (HIRQ) to "1" and will generate an interrupt when starting an SOF with the SOFSTEP bit of the host control register 1 (HCNT1) and the SOF interrupt FRAME comparison register (HFCOMP).
  • Page 301 CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series If you set the CANCEL bit of host control register 1 (HCNT1) to "0", the token set in the host token endpoint register (HTOKEN) is executed after the SOF is sent.
  • Page 302: Error Status

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.8 Error Status USB HOST supports various error information. ■ Error Status ● Stuffing error If continuous 6 bits happen to be "1", one bit of "0" should be inserted in somewhere in the sequence, but the STUFF bit of the host error status register (HERR) is set to "1"...
  • Page 303: Packet End

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.9 Packet End When one packet terminates in USB HOST, if the CMPIRE bit of the host control register 0 (HCNT0) is "1", an interrupt is generated to set the CMPIRQ bit of the host interrupt register (HIRQ) to "1".
  • Page 304: Suspend Resume

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.10 Suspend Resume USB HOST supports suspend and resume operations. ■ Suspend Operation When writing "1" to the SUSP bit of the host state status register (HSTATE), • USB bus high impedance state •...
  • Page 305 CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series Figure 12.5-12 Resume Operation by Device (Full Speed Mode) (2) The simple host pins D+ and D- are detected to be K State. Discovers that HOST pin D + and HOST pin D - become K State.
  • Page 306 CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series Figure 12.5-14 Resume Operation by Device Connection (4) The device is detected being connected. Connect Pin D+ for HOST Pin D- for HOST RWKIRQ bit of HIRQ (RWKIRE=1) HIRQ bit2...
  • Page 307: Cutting Of Device

    CHAPTER 12 USB HOST 12.5 Operation of USB HOST MB90335 Series 12.5.11 Cutting of Device Once both HOST pins D + and D- become "L", the disconnection timer starts, and sets the CSTAT bit of the host state status register (HSTATE) to "0" when both pins detect "L"...
  • Page 308: Each Token Flow Chart Of Usb Host

    CHAPTER 12 USB HOST 12.6 Each Token Flow Chart of USB HOST MB90335 Series 12.6 Each Token Flow Chart of USB HOST The flow chart of each token of USB HOST is as follows. ■ IN, OUT, SETUP Token Figure 12.6-1 Flow Chart at IN, OUT, SETUP Token...
  • Page 309 CHAPTER 12 USB HOST 12.6 Each Token Flow Chart of USB HOST MB90335 Series ■ SOF Token Figure 12.6-2 Flow Chart at SOF Token SOF TOKEN HFRAME change? HFRAME change HEOF change? HEOF change TOKEN execution (Setting TGGL and ENDPT is disregarded.)
  • Page 310: Chapter 13 Pwc Timer

    This chapter describes an overview of PWC timer, the configuration and function of register, and the PWC timer operation and precaution. 13.1 Overview of PWC Timer 13.2 Register of PWC Timer 13.3 Movement of PWC Timer 13.4 Precautions when Using PWC Timer CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 311: Overview Of Pwc Timer

    CHAPTER 13 PWC TIMER 13.1 Overview of PWC Timer MB90335 Series 13.1 Overview of PWC Timer The PWC timer is the multi-functional 16-bit up count timer that has the function to measure the pulse width of input signal. PWC: Pulse Width Count (pulse width measurement) ■...
  • Page 312 CHAPTER 13 PWC TIMER 13.1 Overview of PWC Timer MB90335 Series ■ Block Diagram of PWC Timer Figure 13.1-1 shows the PWC timer block diagram. Figure 13.1-1 Block Diagram of PWC Timer PWCR read Error detection Internal clock (Machine clock/4)
  • Page 313: Register Of Pwc Timer

    CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series 13.2 Register of PWC Timer Configuration and function of the register used for PWC timer are described. ■ Register List of PWC Timer Figure 13.2-1 shows the PWC timer register list.
  • Page 314: Pwc Control Status Register (Pwcsr)

    CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series 13.2.1 PWC Control Status Register (PWCSR) Configuration and function of PWC control status register (PWCSR) are described. ■ PWC Control Status Register (PWCSR) Figure 13.2-2 shows the bit configuration of PWC control status register (PWCSR).
  • Page 315 CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series Table 13.2-2 Functions for Read Operation (Displaying the 16-bit Up-count Timer Operation Status) STRT STOP Operation control functions Timer under suspension (unstarted or measurement completed). [initial value] During timer count operating (during measurement).
  • Page 316 CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series [bit11] OVIR (timer overflow interrupt request flag) This flag indicates the 16-bit up count timer overflowed from FFFF to 0000 . When the timer overflow interrupt factor is permitted (bit10: OVIE = 1) and this bit is set, the timer overflow interrupt request occurs.
  • Page 317 CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series [bit7, bit6] CKS1 and CKS0 (clock selection) Internal count clock can be selected from three types shown in Table 13.2-3. Table 13.2-3 Count Clock of 16 Bit Up Count Timer...
  • Page 318 CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series [bit3] S/C (Measurement mode (single/continuous) selection) The measurement mode is selected. Table 13.2-5 Selection of Measurement Mode of 16-bit Up-count Timer Measurement mode selection At timer mode Pulse width...
  • Page 319: Pwc Data Buffer Register (Pwcr)

    CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series 13.2.2 PWC Data Buffer Register (PWCR) Configuration and function of PWC data buffer register (PWCR) are described. ■ PWC Data Buffer Register (PWCR) Figure 13.2-3 shows the bit configuration of PWC data buffer register (PWCR).
  • Page 320: Pwc Ratio Of Dividing Frequency Control Register (Divr)

    CHAPTER 13 PWC TIMER 13.2 Register of PWC Timer MB90335 Series 13.2.3 PWC Ratio of Dividing Frequency Control Register (DIVR) Configuration and function of PWC Ratio of dividing frequency control register (DIVR) are described. ■ PWC Ratio of Dividing Frequency Control Register (DIVR) Figure 13.2-4 shows the bit configuration of a PWC ratio of dividing frequency control register (DIVR).
  • Page 321: Movement Of Pwc Timer

    CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series 13.3 Movement of PWC Timer The movement of the PPG timer is explained. ■ Outline of PWC Timer Operation The PWC timer, a multi-functional timer based on the 16-bit up count timer has built-in measurement input pin, 8-bit input division, etc.
  • Page 322: Operation Of Pwm Timer Functions

    CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series 13.3.1 Operation of PWM Timer Functions The up count timer enables the reload and one-shot operations. ■ Operation of PWM Timer Functions Performs the count up at every count clock after starting the timer. An interrupt request may occur when an...
  • Page 323: Operation Of Pulse Width Measurement Function

    CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series 13.3.2 Operation of Pulse Width Measurement Function Time cycle between arbiter events of input pulse can be measured by the time. ■ Operation of Pulse Width Measurement Function The pulse width measurement function does not start the count until the set measurement start edge is input after it is started.
  • Page 324: Count Clock Selection And Operation Mode Selection

    CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series 13.3.3 Count Clock Selection and Operation Mode Selection Count clock selection and operation mode selection are described. ■ Count Clock Selection Timer count clock can be selected from three types of internal clock sources by setting the PWCSR bit7 (CKS1) and bit6 (CKS0).
  • Page 325 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series ■ Selects Operation Mode Select each of operation and measurement modes by setting the PWCSR bit. • Operation mode selection: PWCSR bit2, bit1, bit0 (MOD2, MOD1, and MOD0 bits) timer mode/pulse width measurement mode selection, measurement edge decision, etc.
  • Page 326: Startup And Stop Of Timer/Pulse Width Measurement

    CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series 13.3.4 Startup and Stop of Timer/Pulse Width Measurement Start/restart/stop/forced stop of each operation are performed by using the PWCSR bit15 and PWCSR bit14 (STRT and STOP bits). ■ Startup and Stop of Timer/Pulse Width Measurement Functions are separated so that the STRT bit starts and restarts the timer/pulse width measurement and the STOP bit forcibly stops the measurement when "0"...
  • Page 327 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series ● Pulse width measurement mode In the state of measurement starting edge waiting there is no influence in the operation. During the measurement, the count is stopped and the measurement start edge is again waited. In this case, if the measurement termination edge detection and the restart occur at the same time, the measurement termination flag (EDIR) is set and the result is transferred to PWCR in the continuous measurement mode.
  • Page 328: Operation Of Timer Mode

    CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series 13.3.5 Operation of Timer Mode The operation of the timer mode is explained. ■ Clearing Timer The 16-bit up count timer is cleared to be 0000 in the following case: •...
  • Page 329 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series ■ Timer Cycle If 0000 is set to the PWCR in the one-shot operation mode and the timer is started, an overflow occurs after 65536 times counted up to stop the count. The time period from the start to the stop is calculated by...
  • Page 330 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series ■ Operation Flow of Timer Figure 13.3-4 shows the timer operation flow. Figure 13.3-4 Operation Flow of Timer Count clock selection Operation/ Each Measurement settings mode selection Interrupt flag clear...
  • Page 331: Operation Of Pulse Width Measurement Mode

    CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series 13.3.6 Operation of Pulse Width Measurement Mode Operation of pulse width measurement mode is described. ■ Single Measurement and Continuous Measurement Pulse width measurement modes include a mode to perform only one-time measurement and a mode to perform continuous measurements.
  • Page 332 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series ■ Measurement Mode and Counter Operation The measurement mode can be selected from six types depending on the place where the input pulse is measured. The cycle measurement mode is also prepared to arbitrarily divide the input pulse for high- precision measurement of higher frequency pulse width.
  • Page 333 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series Table 13.3-6 The Measurement Mode List (2 / 2) Measurement Measurement mode measured target MOD2 MOD1 MOD0 mode (W: width of a measured pulse) Measurement at Count stop Count start...
  • Page 334 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series ■ Range of Count at Pulse Width/cycle Measurable ranges of pulse width/cycle vary depending on the selected combination of division ratios of count clock and input divider. Table 13.3-7 shows the measurement range list of machine clock when the clock frequency (called φ...
  • Page 335 CHAPTER 13 PWC TIMER 13.3 Movement of PWC Timer MB90335 Series ■ Operation Flow of Pulse Width Measurement Figure 13.3-5 shows the pulse width measurement operation flow. Figure 13.3-5 Operation Flow of Pulse Width Measurement Count clock selection Operation/ Each...
  • Page 336: Precautions When Using Pwc Timer

    CHAPTER 13 PWC TIMER 13.4 Precautions when Using PWC Timer MB90335 Series 13.4 Precautions when Using PWC Timer Precautions when using the PWC timer are described. ■ Precautions when Using PWC Timer ● Notes concerning rewriting register Following bits among PWCSRs are inhibited to be updated during the operation. Always update the bits before starting or after stopping the operation.
  • Page 337 CHAPTER 13 PWC TIMER 13.4 Precautions when Using PWC Timer MB90335 Series ● Minimum pulse width There are following limitations for pulses that can be input to width measurement input pins: • Minimum pulse width: 2 divisions of machine clock (0.25μs or more for 16-MHz machine clock) •...
  • Page 338: Chapter 14 16-Bit Reload Timer

    This chapter describes an overview of 16-bit reload timer, the configuration and functions of register and the 16-bit reload timer operation. 14.1 Overview of 16-bit Reload Timer 14.2 Registers of 16-bit Reload Timer 14.3 Movement of 16-bit Reload Timer CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 339: Overview Of 16-Bit Reload Timer

    CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of 16-bit Reload Timer MB90335 Series 14.1 Overview of 16-bit Reload Timer The 16-bit reload timer provides two functions either one of which can be selected, the internal clock that performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count down by detecting the arbiter edge of pulses input to the external pin.
  • Page 340: Function Of 16-Bit Reload Timer

    CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of 16-bit Reload Timer MB90335 Series 14.1.1 Function of 16-bit Reload Timer This section describes overview and Function of 16-bit reload timer. ■ Operation Modes of 16-bit Reload Timer Clock Mode Counter operation...
  • Page 341 CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of 16-bit Reload Timer MB90335 Series ■ Counter Operation Mode ● Reload mode → FFFF When an underflow (0000 ) occurs during the count down, the count setting value is reloaded to continue the count operation. Interrupt request that can be generated at the underflow occurrence can be also used as an interval timer.
  • Page 342: Block Diagram Of 16-Bit Reload Timer

    CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of 16-bit Reload Timer MB90335 Series 14.1.2 Block Diagram of 16-bit Reload Timer Block Diagram of 16-bit Reload Timer is shown. ■ Block Diagram of 16-bit Reload Timer Figure 14.1-1 Block Diagram of 16-bit Reload Timer...
  • Page 343: Registers Of 16-Bit Reload Timer

    CHAPTER 14 16-BIT RELOAD TIMER 14.2 Registers of 16-bit Reload Timer MB90335 Series 14.2 Registers of 16-bit Reload Timer Configuration and functions of register used for the 16-bit reload timer are described. ■ Register List of 16-bit Reload Timer Figure 14.2-1 is shown the list of the register of 16-bit reload timer.
  • Page 344: Timer Control Status Register 0 (Tmcsr0)

    CHAPTER 14 16-BIT RELOAD TIMER 14.2 Registers of 16-bit Reload Timer MB90335 Series 14.2.1 Timer Control Status Register 0 (TMCSR0) Configuration and functions of timer control status registers 0 (TMCSR0) are described. ■ Timer Control Status Register 0 (TMCSR0) The timer control status registers 0 (TMCSR0) control the operation mode and interrupt of 16-bit reload timer.
  • Page 345 CHAPTER 14 16-BIT RELOAD TIMER 14.2 Registers of 16-bit Reload Timer MB90335 Series [bit9 to bit7] MOD2, MOD1, MOD0 This bit is used to set the operation mode and the I/O pin functions. The input pin functions as a trigger at MOD2=0.
  • Page 346 CHAPTER 14 16-BIT RELOAD TIMER 14.2 Registers of 16-bit Reload Timer MB90335 Series [bit5] OUTL (setting of output level) This bit is used to set the TOT0 pin output level. OUTL and the output pin level reverses in 0/1. OUTL...
  • Page 347 CHAPTER 14 16-BIT RELOAD TIMER 14.2 Registers of 16-bit Reload Timer MB90335 Series [bit1] CNTE (timer counter permission) It is a bit by which the timer counter is permitted. CNTE Function Counter stop [Initial value] Counter permission (startup trigger waiting) [bit0] TRG (Software trigger) It is Software trigger bit.
  • Page 348: 16-Bit Timer Register 0 (Tmr0)/16-Bit Reload Register 0 (Tmrlr0)

    CHAPTER 14 16-BIT RELOAD TIMER 14.2 Registers of 16-bit Reload Timer MB90335 Series 14.2.2 16-bit Timer Register 0 (TMR0)/16-bit Reload Register 0 (TMRLR0) Configuration and functions of 16-bit timer registers 0 (TMR0)/16-bit reload registers 0 (TMRLR0) are described. ■ 16-bit Timer Register 0 (TMR0)/16-bit Reload Register 0 (TMRLR0) Figure 14.2-3 shows the bit configuration of 16-bit timer registers 0 (TMR0)/16-bit reload registers...
  • Page 349 CHAPTER 14 16-BIT RELOAD TIMER 14.2 Registers of 16-bit Reload Timer MB90335 Series ■ 16-bit Reload Register 0 (TMRLR0) Set the initial counter value to the register TMRLR0 in the status the counter operation is inhibited (CNTE = 0 for TMCSR0) regardless of the 16-bit reload timer operation. When the counter operation is permitted (CNTE = 1 for TMCSR0) and the counter is started, the count down is started from the value written in the registers TMRLR0.
  • Page 350: Movement Of 16-Bit Reload Timer

    CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series 14.3 Movement of 16-bit Reload Timer The 16-bit reload timer setting and the counter operation status transition are described. ■ Setting of 16-bit Reload Timer ● Setting of internal clock mode To operate it as an interval timer, the setting shown in Figure 14.3-1 is necessary.
  • Page 351: State Transition Of Counter Operation

    CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series 14.3.1 State Transition of Counter Operation The state transition of the counter operation is shown. ■ State Transition of Counter Operation Figure 14.3-3 State Transition of Counter Operation...
  • Page 352: Operation Of Internal Clock Mode (Reload Mode)

    CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series 14.3.2 Operation of Internal Clock Mode (Reload Mode) It is synchronized with the internal count clock, the 16-bit counter performs the count down, and the counter underflow generates the CPU interrupt request. Also can output toggle waveforms from the timer output pin.
  • Page 353 CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series ● Operation of External trigger When a valid edge (rising edge, falling edge, or both edges can be selected) is input to the TIN0 pin, the counter is started.
  • Page 354 CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series ● Operation of gate input When "1" is set to the count permission bit (CNTE) of timer control status register (TMCSR0) and "1" is set to the software trigger bit (TRG), the count operation is started.
  • Page 355: Operation Of Internal Clock Mode (Single Shot Mode)

    CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series 14.3.3 Operation of Internal Clock Mode (Single Shot Mode) It is synchronized with the internal count clock, the 16-bit counter performs the count down, and the counter underflow generates the CPU interrupt request. Also the TOT0 pin can output rectangular waveforms indicating that counting is going on.
  • Page 356 CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series ● Operation of External trigger When a valid edge (rising edge, falling edge, or both edges can be selected) is input to the TIN0 pin, the counter is started.
  • Page 357 CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series ● Operation of gate input While the valid level ("H" level or "L" level can be selected) is being input to the TIN0 pin, the count operation is performed. Figure 14.3-9 shows the gate input operation in the one-shot mode.
  • Page 358: Event Count Mode

    CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series 14.3.4 Event Count Mode When the input edge from the TIN0 pin is counted, the 16-bit counter is counted down and the counter underflow occurs, the CPU interrupt request is generated. In addition, the toggle waveform or the rectangular waveform can be output from the TOT0 pin.
  • Page 359 CHAPTER 14 16-BIT RELOAD TIMER 14.3 Movement of 16-bit Reload Timer MB90335 Series ● Operation of One-shot mode " → "FFFF When the counter value underflows ("0000 "), the counter stops in the state of "FFFF ". At this moment, if the underflow request flag bit (UF) is set to "1" and the interrupt request output permission bit (INTE) is "1", the interrupt request is generated.
  • Page 360: Chapter 15 8/16-Bit Ppg Timer

    This chapter describes an overview of 8/16-bit PPG timer, the configuration and functions of register, and the 8/16-bit PPG timer operation. 15.1 Overview of 8/16-bit PPG Timer 15.2 Registers of 8/16-bit PPG Timer 15.3 Operation of 8/16-bit PPG Timer CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 361: Overview Of 8/16-Bit Ppg Timer

    • Four external pulse output pins • Four interrupt outputs. Further, the MB90335 series provides 4 channels as the 8-bit PPG that also operate as the 16-bit PPG (2 channels) in the combination of PPG0 + PPG1/PPG2 + PPG3. ■ Overview of 8/16-bit Timer PPG Timer Overview of 8/16-bit PPG timer function is shown below.
  • Page 362: Block Diagram Of 8/16-Bit Ppg Timer

    CHAPTER 15 8/16-BIT PPG TIMER 15.1 Overview of 8/16-bit PPG Timer MB90335 Series 15.1.1 Block Diagram of 8/16-bit PPG Timer Block diagram of ch.0/ch.2 and ch.1/ch.3 of 8/16-bit PPG timer is shown. ■ Block Diagram of 8/16-bit PPG Timer Figure 15.1-1 shows the block diagram of ch.0/ch.2. Figure 15.1-2 shows the block diagram of ch.1/ch.3.
  • Page 363 CHAPTER 15 8/16-BIT PPG TIMER 15.1 Overview of 8/16-bit PPG Timer MB90335 Series Figure 15.1-2 Block Diagram of 8/16-bit PPG Timer (ch.1/ch.3) PPG1/PPG3 Peripheral clock 16 division Output enabled PPG1/PPG3 Peripheral clock 8 division Peripheral clock 4 division Peripheral clock...
  • Page 364: Registers Of 8/16-Bit Ppg Timer

    CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series 15.2 Registers of 8/16-bit PPG Timer Configuration and functions of register used for the 8/16-bit PPG timer are described. ■ Register List of 8/16-bit PPG Timer Figure 15.2-1 shows the register list of 8/16-bit PPG timer.
  • Page 365: Ppg0/Ppg2 Operation Mode Control Register (Ppgc0/Ppgc2)

    CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series 15.2.1 PPG0/PPG2 Operation Mode Control Register (PPGC0/PPGC2) Configuration and functions of PPG0/PPG2 operation mode control register (PPGC0/ PPGC2) are described. ■ PPG0/2 Operation Mode Control Register (PPGC0/PPGC2) The PPG0/PPG2 operation mode control register (PPGC0/PPGC2) selects the operation mode of ch.0/ch.2,...
  • Page 366 CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series [bit4] PIE0: ppg Interrupt Enable (interrupt to PPG0/PPG2 enabled) PPG0/PPG2 interrupt inhibition and permission are controlled. PIE0 Operating State Disables the interrupt Interruption permission • If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is "0", no interrupts are generated.
  • Page 367: Ppg1/Ppg3 Operation Mode Control Register (Ppgc1/Ppgc3)

    CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series 15.2.2 PPG1/PPG3 Operation Mode Control Register (PPGC1/PPGC3) Configuration and functions of PPG1/PPG3 operation mode control register (PPGC1/ PPGC3) are described. ■ PPG1/PPG3 Operation Mode Control Register (PPGC1/PPGC3) The PPG1/PPG3 operation mode control register (PPGC1/PPGC3) selects the operation mode of ch.1/ch.3,...
  • Page 368 CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series [bit13] PE10: ppg output Enable10 (PPG1/PPG3 output pin enabled) Inhibition and permission of pulse output to the external pulse output pin PPG1/PPG3 are controlled. PE10 Operating State...
  • Page 369 CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series [bit10, bit9] MD1, MD0: ppg count Mode (operation mode selection) The operation mode of the PPG timer is selected. Operating mode 8-bit PPG 2 independent mode (The case multiplied by 2 is enabled).
  • Page 370: Ppg0 To Ppg3 Output Control Register (Ppg01/Ppg23)

    CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series 15.2.3 PPG0 to PPG3 Output Control Register (PPG01/PPG23) Configuration and functions of PPG0 to PPG3 output control register (PPG01/PPG23) are described. ■ PPG0 to PPG3 Output Control Register (PPG01/PPG23) Figure 15.2-4 shows the bit configuration of the PPG0 to PPG3 output control registers (PPG01/PPG23).
  • Page 371 CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series [bit4 to bit2] PCM2 to PCM0:ppg Count Mode (count clock selection) These bits select the down counter operation clock of ch.0 and ch.2. PCM2 PCM1 PCM0 Operating mode Peripheral Clock (41.6 ns machine clock 24 MHz time)
  • Page 372: Ppg Reload Registers (Prll0 To Prll3, Prlh0 To Prlh3)

    CHAPTER 15 8/16-BIT PPG TIMER 15.2 Registers of 8/16-bit PPG Timer MB90335 Series 15.2.4 PPG Reload Registers (PRLL0 to PRLL3, PRLH0 to PRLH3) Configuration and functions of PPG reload registers (PRLL0 to PRLL3, PRLH0 to PRLH3) are described. ■ PPG Reload Registers (PRLL0 to PRLL3, PRLH0 to PRLH3) Figure 15.2-5 shows the bit configuration of PPG reload registers (PRLL0 to PRLL3, PRLH0 to PRLH3).
  • Page 373: Operation Of 8/16-Bit Ppg Timer

    The 8/16-bit PPG timer has 3-type operation modes in total, the 2-channel independent mode, the 8-bit prescaler + 8-bit PPG mode, and the 16-bit PPG mode (MB90335 series have 2 channels for each mode). The 2-channel independent mode is a mode to allow an independent 2-channel operation as the 8-bit PPG.
  • Page 374 CHAPTER 15 8/16-BIT PPG TIMER 15.3 Operation of 8/16-bit PPG Timer MB90335 Series ■ PPG Output Operation The 8/16-bit PPG timer is started to begin the count when both the bit7 (PEN0) of PPGC0 register for ch.0 (ch.2) PPG and the bit15 (PEN1) of PPGC1 register for ch.1 (ch.3) PPG are set to "1". After the operation started, when "0"...
  • Page 375 CHAPTER 15 8/16-BIT PPG TIMER 15.3 Operation of 8/16-bit PPG Timer MB90335 Series ■ Count Clock Selection The count clock used for 8/16-bit PPG timer operation uses the peripheral clock and the time-base counter input to allow 6 types of count clock input selection.
  • Page 376 The 8/16-bit PPG timer interrupt becomes active when the reload value is counted out and a borrow occurs. In the 8-bit PPG 2channel mode or the 8-bit prescaler + 8-bit PPG mode (each of MB90335 series has 2 channels), each interrupt request is generated by each borrow. In the 16-bit PPG mode, however, the PUF0 and the PUF1 are simultaneously set by the 16-bit counter borrow.
  • Page 377 CHAPTER 15 8/16-BIT PPG TIMER 15.3 Operation of 8/16-bit PPG Timer MB90335 Series ■ Writing Timing to Reload Register In any modes other than the 16-bit PPG mode, the word transfer instruction is recommended to write data into the reload registers PRLL and PRLH. When the data item is written in the register by using the byte transfer instructions for two times, an unexpected pulse width output may be generated depending on the timing.
  • Page 378: Chapter 16 Dtp/External Interrupt

    This chapter describes an overview of DTP/external interrupt, the configuration and functions of register, and the DTP/external interrupt operation. 16.1 Overview of DTP/External Interrupt 16.2 Register of DTP/External Interrupt 16.3 Operation of DTP/External Interrupt 16.4 Precaution of Using DTP/External Interrupt CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 379: Overview Of Dtp/External Interrupt

    CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.1 Overview of DTP/External Interrupt MB90335 Series 16.1 Overview of DTP/External Interrupt The DTP (Data Transfer Peripheral) is located between peripherals existing out of the device and the F MC-16LX CPU. It is the peripheral control section that receives a DMA request or an interrupt request generated by the external peripheral, reports it to the MC-16LX CPU, and starts the μDMAC or the interrupt processing.
  • Page 380: Register Of Dtp/External Interrupt

    CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.2 Register of DTP/External Interrupt MB90335 Series 16.2 Register of DTP/External Interrupt This section describes the configuration and functions of registers used for the DTP and external interrupts. ■ Register List of DTP/External Interrupt Figure 16.2-1 shows the register list of the DTP/external interrupts.
  • Page 381 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.2 Register of DTP/External Interrupt MB90335 Series ■ DTP/Interruption Factor Register (EIRR: External Interrupt Request Register) Figure 16.2-3 shows the bit configuration of DTP/interruption factor register (EIRR). Figure 16.2-3 Bit Configuration of DTP/interruption Factor Register (EIRR)
  • Page 382 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.2 Register of DTP/External Interrupt MB90335 Series Table 16.2-1 ELVR allocation (LA0 to LA7, LB0 to LB7) Operation There is a demand at "L" level. There is a demand at "H" level. Request present at the rising edge...
  • Page 383: Operation Of Dtp/External Interrupt

    CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 Operation of DTP/External Interrupt MB90335 Series 16.3 Operation of DTP/External Interrupt This section describes the Operation of DTP/External Interrupt. ■ External Interrupt Operation If a request set by the ELVR register at the corresponding pin is input after setting an external interrupt request, this resource issues an interrupt request signal for the interrupt controller.
  • Page 384 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 Operation of DTP/External Interrupt MB90335 Series Figure 16.3-2 Timing to Cancel the External Interrupt Request at the DTP Operation Termination Edge request or "H" level request Interrupt factor Note : μDMAC Descriptor Internal operation I/O register...
  • Page 385: Precaution Of Using Dtp/External Interrupt

    CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 Precaution of Using DTP/External Interrupt MB90335 Series 16.4 Precaution of Using DTP/External Interrupt Notes DTP/an external interruption is used are explained. ■ Condition of Peripheral Equipment Connected Outside The external peripheral device that the DTP can support must automatically clear the request at the transfer execution.
  • Page 386 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 Precaution of Using DTP/External Interrupt MB90335 Series Figure 16.4-2 Interrupt Factor when Enabling the Interrupt and the Interrupt Request for the Interrupt Controller Interrupt factor (At detecting "H" level) Interrupt request Cancel the interrupt request...
  • Page 387 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 Precaution of Using DTP/External Interrupt MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 388: Chapter 17 Extended I/O Serial Interface

    I/O serial interface. 17.1 Outline of Extended I/O Serial Interface 17.2 Register in Extended I/O Serial Interface 17.3 Operation of Extended I/O Serial Interface CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 389: Outline Of Extended I/O Serial Interface

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.1 Outline of Extended I/O Serial Interface MB90335 Series 17.1 Outline of Extended I/O Serial Interface The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit x 1 channel configured clock synchronization scheme. LSB first/ MSB first can be selected in data transfer.
  • Page 390: Register In Extended I/O Serial Interface

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series 17.2 Register in Extended I/O Serial Interface The configuration and functions of registers used in the extended I/O serial interface are described. ■ List of Register in Extended I/O Serial Interface Figure 17.2-1 shows the list of register in extended I/O serial interface.
  • Page 391: Serial Mode Control Status Register (Smcs)

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series 17.2.1 Serial Mode Control Status Register (SMCS) The configuration and functions of Serial mode control status register (SMCS) is described. ■ Serial Mode Control Status Register (SMCS) Serial mode control status register (SMCS) is a register which controls the transfer operating mode of serial I/O.
  • Page 392 CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series Table 17.2-2 Example of Settings of the Communication Prescaler (SDCR) (Machine clock) Machine cycle (Recommended Setting) DIV3 DIV2 DIV1 DIV0 3 MHz 6 MHz 12 MHz 24 MHz Initialized to "000...
  • Page 393 CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series [bit9] STOP (stop bit) This bit forcibly suspends serial transfer. When this bit is "1", the state changes into HALT based on STOP=1. STOP Operation...
  • Page 394 CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series [bit2] BDS: Bit Direction Selection (transfer direction selection) On input and output of the serial data, Select either of the following alternatives: transfer in ascending order from the least significant bit (LSB first);...
  • Page 395: Serial Data Register (Sdr)

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series 17.2.2 Serial Data Register (SDR) The configuration and functions of Serial data register (SDR) are described. ■ Serial Data Register (SDR) Figure 17.2-3 shows the bit configuration of the serial data register (SDR).
  • Page 396: Communication Prescaler Control Register (Sdcr)

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series 17.2.3 Communication Prescaler Control Register (SDCR) The configuration and functions of communication prescaler control register (SDCR) are described. ■ Communication Prescaler Control Register (SDCR) Figure 17.2-4 shows the bit configuration of communication prescaler control register (SDCR).
  • Page 397 CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.2 Register in Extended I/O Serial Interface MB90335 Series Note: In the case of making changes to the rate of division, allow for two divisions of intervals as the duration of stabilization of the clock before communication.
  • Page 398: Operation Of Extended I/O Serial Interface

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series 17.3 Operation of Extended I/O Serial Interface Extended I/O interface consists of a serial mode control status register (SMCS) and a serial data register (SDR) and is used to input and output 8-bit serial data.
  • Page 399: Shift Clock Mode

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series 17.3.1 Shift Clock Mode Shift clock includes two types of modes; one is Internal Shift Clock Mode, the other is External Shift Clock Mode, both of which are specified by settings of SMCS. Please switch the mode with serial I/O stopped.
  • Page 400: Operation State Of Serial I/O

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series 17.3.2 Operation State of Serial I/O The states of serial I/O operation includes the following 4 types of states; STOP, HALT, R/W WAIT of SDR, and TRANSFER.
  • Page 401 CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series ● Transfer State It is a state to do the serial transfer by BUSY = 1. MODE bit triggers the transition to the state of HALT and R/W WAIT respectively.
  • Page 402: Start/Stop Timing Of Shift Operation And Timing Of I/O

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series 17.3.3 Start/Stop Timing of Shift Operation and Timing of I/O Start/stop timing of shift operation and timing of I/O is described. ■ Start/stop Timing of Shift Operation and Timing of I/O •...
  • Page 403 CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series ● For instruction shift in external shift clock mode (LSB first) In instruction shift, when "1" is written to the PDR6:P64, "H" is output, and when "0" is written, "L" is output (where external shift clock mode is selected, and SCOE=0).
  • Page 404: Interrupt Function

    CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series 17.3.4 Interrupt Function Extended I/O serial interface can generate the interrupt request to the CPU. ■ Interruption Function of Extended I/O Serial Interface Upon completion of data transfer, SIR bit indicating an interrupt flag is set, and when SIE bit of the SMCS enabling interrupts is "1", the interrupt request is output to the CPU.
  • Page 405 CHAPTER 17 EXTENDED I/O SERIAL INTERFACE 17.3 Operation of Extended I/O Serial Interface MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 406: Chapter 18 Uart

    18.1 Overview of UART 18.2 Block Diagram of UART 18.3 UART Pins 18.4 Register of UART 18.5 UART Interrupt 18.6 UART Baud Rate 18.7 Explanation of Operation of UART 18.8 Notes on Using UART 18.9 Example of UART Programming CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 407: Overview Of Uart

    CHAPTER 18 UART 18.1 Overview of UART MB90335 Series 18.1 Overview of UART UART is a general purpose serial data communication interface for synchronous or asynchronous (start-stop synchronization) communications with external devices. Not only the typical function of bidirectional communication (normal mode), but also the function of master/slave communication (multiprocessor mode: only supported master side) are supported.
  • Page 408 CHAPTER 18 UART 18.1 Overview of UART MB90335 Series Table 18.1-2 UART Operation Modes Data length Synchronous Length of Operating mode Without type Stop Bit With Parity Parity Normal mode 7 bits or 8 bits Asynchronous 1 bit Multiprocessor mode...
  • Page 409: Block Diagram Of Uart

    CHAPTER 18 UART 18.2 Block Diagram of UART MB90335 Series 18.2 Block Diagram of UART UART is composed of the following block. ■ Block Diagram of UART Figure 18.2-1 Block Diagram of UART Control bus Dedicated baud Receive interrupt signal...
  • Page 410 CHAPTER 18 UART 18.2 Block Diagram of UART MB90335 Series ● Clock selector Dedicated baud rate generator, selecting the send and receive clock from external input clocks. ● Reception Control Circuit The reception control circuit is configured with the reception bit counter, start bit detecting circuit, and reception parity counter.
  • Page 411 CHAPTER 18 UART 18.2 Block Diagram of UART MB90335 Series ● Serial input data register 0, 1 (SIDR0, SIDR1) The register retains the receive data. The serial input is converted and then stored in this register. ● Serial output data register 0, 1 (SODR0, SODR1) The register sets the transmit data.
  • Page 412: Uart Pins

    CHAPTER 18 UART 18.3 UART Pins MB90335 Series 18.3 UART Pins The pin of UART is shown. ■ UART Pins The UART pins also serve as general-purpose ports. Table 18.3-1 shows the functions of pins, input-output formats, and settings in using UART, etc.
  • Page 413: Register Of Uart

    CHAPTER 18 UART 18.4 Register of UART MB90335 Series 18.4 Register of UART The list of the register of UART is shown. ■ List of UART Register Figure 18.4-1 List of UART Register Address bit8 bit7 bit0 bit15 ch.0 : 000021...
  • Page 414: Serial Control Register 0, 1 (Scr0, Scr1)

    CHAPTER 18 UART 18.4 Register of UART MB90335 Series 18.4.1 Serial Control Register 0, 1 (SCR0, SCR1) Serial control registers 0, 1 (SCR0, SCR1) are responsible for setting parity, selecting the stop bit length and data length, selecting the frame data format in mode 1, clearing receiving error flags, and enabling/disabling send and receive operations.
  • Page 415 CHAPTER 18 UART 18.4 Register of UART MB90335 Series Table 18.4-1 Functional Description of Each Bit in Serial Control Register 0, 1 (SCR0, SCR1) Bit name Functions Specify whether to add (at sending) or detect (at receiving) a parity bit.
  • Page 416: Serial Mode Register 0, 1 (Smr0, Smr1)

    CHAPTER 18 UART 18.4 Register of UART MB90335 Series 18.4.2 Serial Mode Register 0, 1 (SMR0, SMR1) The serial mode registers 0, 1 (SMR0, SMR1) are responsible for selecting operation modes, setting pins related to serial data and cock to be enabled or disabled, and setting how many bit to transfer ranging from 1 to 8 bits, setting the serial clock output level in the inactive operation (fixed to "L"...
  • Page 417 CHAPTER 18 UART 18.4 Register of UART MB90335 Series Table 18.4-2 Functional Description of Each Bit in Serial Mode Register 0, 1 (SMR0, SMR1) Bit name Functions Set Operating mode Notes: MD1, MD0: - In operation mode 1, the device can be used only as the master for master/slave...
  • Page 418: Serial Status Register 0, 1 (Ssr0, Ssr1)

    CHAPTER 18 UART 18.4 Register of UART MB90335 Series 18.4.3 Serial Status Register 0, 1 (SSR0, SSR1) The serial status registers 0, 1 (SSR0, SSR1) are responsible for checking sending and receiving and the states of errors, and setting interrupts to be enabled or disabled.
  • Page 419 CHAPTER 18 UART 18.4 Register of UART MB90335 Series Table 18.4-3 Description of Each Bit of the Serial Status Registers 0, 1 (SSR0, SSR1) (1 / 2) Bit name Functions • Detect a parity error of receiving data. • This bit is set to "1" when a parity error occurs.
  • Page 420 CHAPTER 18 UART 18.4 Register of UART MB90335 Series Table 18.4-3 Description of Each Bit of the Serial Status Registers 0, 1 (SSR0, SSR1) (2 / 2) Bit name Functions • Enable or disable send interrupt. TIE: • When set to "1": If the data written to the serial output data registers 0, 1 is sent to the...
  • Page 421: Serial Input Data Register 0, 1 (Sidr0, Sidr1) And Serial Output Data Register 0, 1 (Sodr0, Sodr1)

    CHAPTER 18 UART 18.4 Register of UART MB90335 Series 18.4.4 Serial Input Data Register 0, 1 (SIDR0, SIDR1) and Serial Output Data Register 0, 1 (SODR0, SODR1) Serial input data and serial output data registers are located in the same address. They function as a serial input data register in reading, while in writing as a serial output data register.
  • Page 422 CHAPTER 18 UART 18.4 Register of UART MB90335 Series ■ Serial Output Data Register 0, 1 (SODR0, SODR1) Figure 18.4-6 shows the bit configuration of serial output data register. Figure 18.4-6 Serial Output Data Register 0, 1 (SODR0, SODR1) Address...
  • Page 423: Uart Prescaler Control Register 0, 1 (Utcr0, Utcr1) And Uart Prescaler Reload Register 0, 1 (Utrlr0, Utrlr1)

    CHAPTER 18 UART 18.4 Register of UART MB90335 Series 18.4.5 UART Prescaler Control Register 0, 1 (UTCR0, UTCR1) and UART Prescaler Reload Register 0, 1 (UTRLR0, UTRLR1) UART prescaler control registers 0, 1 (UTCR0, UTCR1) are responsible of setting start- up/halt of the prescaler, forced reset, and selecting clock sources.
  • Page 424 CHAPTER 18 UART 18.4 Register of UART MB90335 Series [bit13] CKS: clock source selection bit The clock source is selected. 0: Dedicated baud rate generator 1: External clock [bit12] Reserved: reserved bit It is Reserved bit. Be sure to set this bit to "0".
  • Page 425: Uart Interrupt

    CHAPTER 18 UART 18.5 UART Interrupt MB90335 Series 18.5 UART Interrupt The UART support reception and transmission interrupts, capable of generating an interrupt request in the following conditions: • Where the receiving data is set to the serial input data registers 0, 1 (SIDR0, SIDR1), or an receiving error has occurred.
  • Page 426 CHAPTER 18 UART 18.5 UART Interrupt MB90335 Series ● Transmission Interrupt When sending data is sent from the serial output data registers 0, 1 (SODR0, SODR1) to the sending shift register, then the sending data empty flag bit (SSR0, SSR1: TDRE) is set to "1". When sending interrupts are enabled (SSR0, SSR1: TIE=1), a sending interrupt request is generated.
  • Page 427: Receive Interrupt Generation And Flag Set Timing

    CHAPTER 18 UART 18.5 UART Interrupt MB90335 Series 18.5.1 Receive Interrupt Generation and Flag Set Timing Interrupts during reception are one generated upon completion of reception (SSR0, SSR1: RDRF) and one generated upon occurrence of a reception error (SSR0, SSR1: PE, ORE, FRE).
  • Page 428 CHAPTER 18 UART 18.5 UART Interrupt MB90335 Series Figure 18.5-1 Timing of Receiving Operation and Set of Flags Receive data D7/P (Operation mode 0) Receive data (Operation mode 1) Receive data (Operation mode 2) PE, ORE, FRE RDEF Receive Interrupt generation * : PE flag cannot be use in mode 1.
  • Page 429: Transmit Interrupt Generation And Flag Set Timing

    CHAPTER 18 UART 18.5 UART Interrupt MB90335 Series 18.5.2 Transmit Interrupt Generation and Flag Set Timing An interrupt during transmission is generated when serial output data register 0, 1 (SODR0, SODR1) becomes empty, or ready to accommodate the next data to transmit.
  • Page 430 CHAPTER 18 UART 18.5 UART Interrupt MB90335 Series ● Timing transmission interrupt request generation When sending interrupts are enabled (SSR0, SSR1: TIE=1) and if the sending data empty flag bit (SSR0, SSR1: TDRE) is set to "1", a sending interrupt request is generated.
  • Page 431: Uart Baud Rate

    CHAPTER 18 UART 18.6 UART Baud Rate MB90335 Series 18.6 UART Baud Rate The sending and receiving clocks of UART has the following alternatives. • Internal clock (reload counter) • External clock (reload counter) • External clock (clock input to SCK pin) ■...
  • Page 432: Baud Rate Of The Uart Internal Clock Using The Dedicated Baud Rate Generator

    CHAPTER 18 UART 18.6 UART Baud Rate MB90335 Series 18.6.1 Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator Indicates baud rates possible to set when selecting a dedicated baud rate generator, as an UART transfer clock.
  • Page 433: Baud Rate Of The External Clock Using The Dedicated Baud Rate Generator

    CHAPTER 18 UART 18.6 UART Baud Rate MB90335 Series 18.6.2 Baud Rate of the External Clock Using the Dedicated Baud Rate Generator Indicates baud rates possible to set when a dedicated baud rate generator of an external clock is selected, as UART transfer clock. It is used in the asynchronous modes.
  • Page 434: Baud Rate Of The External Clock (One-To-One Mode)

    CHAPTER 18 UART 18.6 UART Baud Rate MB90335 Series 18.6.3 Baud Rate of the External Clock (One-to-one Mode) Indicates the formula for the settings and the baud rates for selecting the external clock, as UART transfer clock. It is used in the clock synchronous modes.
  • Page 435: Explanation Of Operation Of Uart

    CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series 18.7 Explanation of Operation of UART UART supports the master/slave connection based communication function (operation mode 1) as well as the typical bidirectional serial communication function (operation mode 0, operation mode 2).
  • Page 436 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series ● Synchronous type Either asynchronous method or (start-stop synchronization) clock synchronous method can be selected. ● Signal type Data in NRZ (Non Return to Zero) format is only supported.
  • Page 437: Operation In Asynchronous Mode (Operation Mode 0 Or Operation Mode1)

    CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series 18.7.1 Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode1) The UART uses asynchronous transfer when used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode).
  • Page 438 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series ● Transmission Operation • Sending data is written in the serial output data registers 0, 1 (SODR0, SODR1) in the state of "1" being set to the sending data empty flag bit (SSR0, SSR1: TDRE).
  • Page 439 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series Figure 18.7-2 Sending and Receiving Data when Parity Bits are Valid When receiving by even parity SIN0, SIN1 Parity error generation (SCR0, SCR1 : P=0) 1 0 1 1 0 0 0 0...
  • Page 440: Operation In Synchronous Mode (Operation Mode 2)

    CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series 18.7.2 Operation in Synchronous Mode (Operation Mode 2) The UART uses clock-synchronous transfer when used in operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation Mode 2) ●...
  • Page 441 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series ● Specification of serial clock output level at inoperative Serial clock output level (SMR: SCKL) at the clock synchronous mode and inoperative can be set. Figure 18.7-4 Setting of Serial Clock Output Level at Inoperative...
  • Page 442 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series [Serial control register 0, 1 (SCR0, SCR1)] : "0" P, SBL, A/D : These bits do not have the meaning. : "1"(8-bit data) : "0" (for initialization, error flags cleared).
  • Page 443: Bidirectional Communication Function (Normal Mode)

    CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series 18.7.3 Bidirectional Communication Function (Normal Mode) In the mode 0 and 2, typical serial bidirectional communication on the one-to-one connection is available. The communication clock mode becomes asynchronous for the operation mode 0, synchronous for the operation mode 2.
  • Page 444 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series ● Communication procedure Communications start at any timing from the transmitting side when transmit data is provided. On the transmission side, load transmit data into the serial output data register 0, 1 (SODR0, SODR1) and set the transmission enable bit (SCR0, SCR1:TXE) in the serial control register to "1"...
  • Page 445: Master/Slave Mode Communication Function (Multi-Processor Mode)

    CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series 18.7.4 Master/Slave Mode Communication Function (Multi-processor mode) Operation mode 1 allows communication between multiple CPUs connected in a master/ slave configuration. However, this is available only as master. ■ Master/Slave Mode Communication Function To operate UART in the multi-processor mode (operation mode 1), the settings described in Figure 18.7-8...
  • Page 446 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series ● Function Selection When it comes to master/slave communication, select the operation mode and data transfer direction, as shown in Table 18.7-2. Since the parity check function cannot be used in operation mode 1, set the parity enable bit (SCR0, SCR1:PEN) to "0".
  • Page 447 CHAPTER 18 UART 18.7 Explanation of Operation of UART MB90335 Series Figure 18.7-10 Flowchart for Master/Slave Communications (Master CPU) START Setting operating mode to "1" Set SIN pin to Serial data input Set 1 byte data (address data) selecting the slave...
  • Page 448: Notes On Using Uart

    CHAPTER 18 UART 18.8 Notes on Using UART MB90335 Series 18.8 Notes on Using UART Use of the UART requires the following cautions. ■ Notes on Using UART ● Enabling sending and receiving • The bits indicating that sending operation is enabled (SCR0, SCR1: TXE) and that receiving operation is enabled (SCR0, SCR1: RXE) is provided for sending and receiving respectively.
  • Page 449: Example Of Uart Programming

    CHAPTER 18 UART 18.9 Example of UART Programming MB90335 Series 18.9 Example of UART Programming This section provides program example for UART. ■ Example of UART Programming ● Processing specification Perform serial transmission/reception using the bidirectional communication function (normal mode) of the UART.
  • Page 450 CHAPTER 18 UART 18.9 Example of UART Programming MB90335 Series I:SCR0, #00110011B ; Parity none and stop bit 2 bits ; Data length 8 bits and reception clear error flag ; Enables the transmission/reception operation I:SSR0, #00000010B ; sending interrupt disabled, receiving interrupt ;...
  • Page 451 CHAPTER 18 UART 18.9 Example of UART Programming MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 452: Chapter 19 I 2 C Interface

    This chapter gives an overview of I C interface, the configuration and functions of registers, and operations of I C interface. 19.1 I C Interface Outline 19.2 I C Interface Register 19.3 I C Interface Operation CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 453: I 2 C Interface Outline

    CHAPTER 19 I C INTERFACE 19.1 I C Interface Outline MB90335 Series 19.1 C Interface Outline C interface is Serial I/O by which Inter IC BUS is supported. Operates as the master/ slave devices on I C bus. ■ I...
  • Page 454 CHAPTER 19 I C INTERFACE 19.1 I C Interface Outline MB90335 Series ■ Block Diagram of I C Interface Figure 19.1-1 shows the block diagram of I C interface. Figure 19.1-1 Block Diagram of I C Interface ICCR0 C enable...
  • Page 455: I 2 C Interface Register

    CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series 19.2 C Interface Register The configuration and functions of registers used in the I C interface are described. ■ Register List of I C Interface Figure 19.2-1 Register List of I...
  • Page 456: I 2 C Bus Status Register 0 (Ibsr0)

    CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series 19.2.1 C Bus Status Register 0 (IBSR0) The configuration and functions of I C bus status register 0 (IBSR0) are described. ■ I C Bus Status Register 0 (IBSR0) Figure 19.2-2 shows the bit configuration of I...
  • Page 457 CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series [bit4] LRB: Last Received bit It is the acknowledgement storage bit. Stores the acknowledge from the receiver. Reception is acknowledged Reception is not acknowledged It is cleared by detecting the start condition or the stop condition.
  • Page 458: I 2 C Bus Control Register 0 (Ibcr0)

    CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series 19.2.2 C Bus Control Register 0 (IBCR0) The configuration and functions of I C bus control register 0 (IBCR0) are described. ■ I C Bus Control Register 0 (IBCR0) Figure 19.2-3 shows the bit configuration of bus control register 0(IBCR0).
  • Page 459 CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series [bit13] SCC: Start Condition Continue It is a start condition generation bit. (at writing) No effect on operation A start condition is regenerated on master transmission. This bit is always "0" at the beginning of reading.
  • Page 460 CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series [bit8] INT: INTerrupt It is transfer stop interrupt request flag bit. (at writing) Clear Transfer stop interrupt request flag. No effect on operation (at reading) Transfer has not been finished yet.
  • Page 461 CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series • Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur When an instruction which generates a start condition by enabling I C operation (EN bit=1) is executed (setting the MSS bit in the IBCR0 register to "1") with the I...
  • Page 462 CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR0) to "1". Wait* for the time for three-bit data transmission at the I transfer frequency set in the clock control register (ICCR0).
  • Page 463 CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series ■ Notes on Use of I C Bus Control Register 0 (IBCR0) The following care should be taken to conflicts among SCC bit, MSS bit, and INT bit.
  • Page 464: I 2 C Bus Clock Control Register 0 (Iccr0)

    CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series 19.2.3 C Bus Clock Control Register 0 (ICCR0) The configuration and functions of I C bus clock control register 0 (ICCR0) are described. ■ I C Bus Clock Control Register 0 (ICCR0) Figure 19.2-7 shows the bit configuration of I...
  • Page 465 CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series Table 19.2-1 Setting of Serial Clock Frequency FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 466: I 2 C Bus Address Register 0 (Iadr0)

    CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series 19.2.4 C Bus Address Register 0 (IADR0) The configuration and functions of I C bus address register 0 (IADR0) are described. ■ I C Bus Address Register 0 (IADR0) Figure 19.2-8 shows the bit configuration of the I...
  • Page 467: I 2 C Bus Data Register 0 (Idar0)

    CHAPTER 19 I C INTERFACE 19.2 I C Interface Register MB90335 Series 19.2.5 C Bus Data Register 0 (IDAR0) The configuration and functions of I C bus data register 0 (IDAR0) are described. ■ I C Bus Data Register 0 (IDAR0) Figure 19.2-9 shows the bit configuration of the I...
  • Page 468: I 2 C Interface Operation

    CHAPTER 19 I C INTERFACE 19.3 I C Interface Operation MB90335 Series 19.3 C Interface Operation For I C bus, 1 serial data line (SDA0), 1 serial clock line (SCL0), and 2 bidirectional bus lines are responsible for communication. I C interface, which has 2 open drain input- output pins (SDA0 and SCL0) to them, allows wired logic.
  • Page 469 C INTERFACE 19.3 I C Interface Operation MB90335 Series ■ Acknowledge The receiver send the acknowledge to the sender. During data reception, ACK bit can specify acknowledgement is necessary or not. During the data sending, the acknowledge from the receiver is stored in the LRB bit.
  • Page 470: Transfer Flow Of I C Interface

    CHAPTER 19 I C INTERFACE 19.3 I C Interface Operation MB90335 Series 19.3.1 Transfer Flow of I C Interface Figure 19.3-1 shows the 1-byte transfer flow from master to slave, and Figure 19.3-2 shows the 1-byte transfer flow from slave to master.
  • Page 471 CHAPTER 19 I C INTERFACE 19.3 I C Interface Operation MB90335 Series Figure 19.3-2 1-byte Transfer Flow from Slave to Master Master Slave Start IDAR0: Writing MSS: Writing "1" Start condition BB set,TRX set BB set,TRX set Address data transfer...
  • Page 472: Mode Flow Of I C Interface

    CHAPTER 19 I C INTERFACE 19.3 I C Interface Operation MB90335 Series 19.3.2 Mode Flow of I C Interface Figure 19.3-3 shows the flow of mode transitions for the I C interface. ■ Flow of I C Interface Mode Transitions Figure 19.3-3 I...
  • Page 473: Operation Flow Of I 2 C Interface

    CHAPTER 19 I C INTERFACE 19.3 I C Interface Operation MB90335 Series 19.3.3 Operation Flow of I C Interface Figure 19.3-4 shows the operation flow of a master send/receive program (with interrupts) for the I C interface. Figure 19.3-5 shows the operation flow of the slave program (with interrupts) for the I C interface.
  • Page 474 CHAPTER 19 I C INTERFACE 19.3 I C Interface Operation MB90335 Series Figure 19.3-5 Operation Flow of the Slave Program (with Interrupts) for the I C Interface Main routine Interrupt routine Start Start Clear the transfer end Clear the bus error...
  • Page 475 CHAPTER 19 I C INTERFACE 19.3 I C Interface Operation MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 476: Chapter 20 Rom Mirror Function Selection Module

    CHAPTER 20 ROM MIRROR FUNCTION SELECTION MODULE This chapter describes the ROM mirror function selection module. 20.1 Overview of ROM Mirror Function Select Module 20.2 ROM Mirror Function Select Register (ROMM) CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 477: Overview Of Rom Mirror Function Select Module

    CHAPTER 20 ROM MIRROR FUNCTION SELECTION MODULE 20.1 Overview of ROM Mirror Function Select Module MB90335 Series 20.1 Overview of ROM Mirror Function Select Module The ROM mirror function selection module is used to select via register settings an FF bank in ROM, whose contents can be viewed via 00 bank.
  • Page 478: Rom Mirror Function Select Register (Romm)

    CHAPTER 20 ROM MIRROR FUNCTION SELECTION MODULE 20.2 ROM Mirror Function Select Register (ROMM) MB90335 Series 20.2 ROM Mirror Function Select Register (ROMM) The configuration and functions of ROM Mirror Function Select Register (ROMM) are described. ■ ROM Mirror Function Select Register (ROMM) Figure 20.2-1 shows the bit configuration of ROM mirror function select register (ROMM).
  • Page 479 CHAPTER 20 ROM MIRROR FUNCTION SELECTION MODULE 20.2 ROM Mirror Function Select Register (ROMM) MB90335 Series FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 480: Chapter 21 Address Match Detection Function

    21.1 Overview of Address Match Detection Function 21.2 Block Diagram of Address Match Detection Function 21.3 Configuration of Address Match Detection Function 21.4 Explanation of Operation of Address Match Detection Function 21.5 Program Example of Address Match Detection Function CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 481: Overview Of Address Match Detection Function

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.1 Overview of Address Match Detection Function MB90335 Series 21.1 Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detect address setting...
  • Page 482: Block Diagram Of Address Match Detection Function

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.2 Block Diagram of Address Match Detection Function MB90335 Series 21.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Program address detection control status register (PACSR) •...
  • Page 483: Configuration Of Address Match Detection Function

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Configuration of Address Match Detection Function MB90335 Series 21.3 Configuration of Address Match Detection Function This section details the registers used by the address match detection function. ■ List of Registers and Initial Values of Address Match Detection Function Figure 21.3-1 List of Registers and Initial Values of Address Match Detection Function...
  • Page 484: Program Address Detection Control Status Register (Pacsr)

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Configuration of Address Match Detection Function MB90335 Series 21.3.1 Program Address Detection Control Status Register (PACSR) The program address detection control status register (PACSR) enables or disables output of an interrupt at an address match. When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated.
  • Page 485 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Configuration of Address Match Detection Function MB90335 Series Table 21.3-1 Functions of Address Detection Control Register (PACSR) Bit Name Function bit7 to Reserved: reserved bits Always set to "0". bit4 The address match detection operation with the detect address setting register 1 (PADR1) is enabled or disabled.
  • Page 486: Program Address Detection Registers (Padr0, Padr1)

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Configuration of Address Match Detection Function MB90335 Series 21.3.2 Program Address Detection Registers (PADR0, PADR1) The value of an address to be detected is set in the program address detection registers. When the address of the instruction processed by the program matches the address set in the program address detection registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed.
  • Page 487 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Configuration of Address Match Detection Function MB90335 Series ■ Functions of Program Address Detection Registers • There are two Program address detection registers (PADR0, PADR1) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits.
  • Page 488: Explanation Of Operation Of Address Match Detection Function

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Explanation of Operation of Address Match Detection Function MB90335 Series 21.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the...
  • Page 489: Example Of Using Address Match Detection Function

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Explanation of Operation of Address Match Detection Function MB90335 Series 21.4.1 Example of Using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function.
  • Page 490 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Explanation of Operation of Address Match Detection Function MB90335 Series ■ E PROM Memory Map Figure 21.4-3 shows the allocation of the patch program and data at storing the patch program in E PROM.
  • Page 491 ● INT9 Interrupt processing • Interrupt processing is performed by the INT9 instruction. The MB90335 series has no interrupt request flag by address match detection. Therefore, if the stack information in the program counter is discarded, the detect address cannot be checked. When checking the detect address, check the value of program counter stacked in the interrupt processing routine.
  • Page 492 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Explanation of Operation of Address Match Detection Function MB90335 Series ■ Operation of Address Match Detection Function at Storing Patch Program in PROM Figure 21.4-4 shows the operation of the address match detection function at storing the patch program in E PROM.
  • Page 493 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Explanation of Operation of Address Match Detection Function MB90335 Series ■ Flow of Patch Processing Figure 21.4-5 shows the flow of patch processing using the address match detection function. Figure 21.4-5 Flow of Patch Processing...
  • Page 494: Program Example Of Address Match Detection Function

    CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.5 Program Example of Address Match Detection Function MB90335 Series 21.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. ■ Program Example for Address Match Detection Function ●...
  • Page 495 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.5 Program Example of Address Match Detection Function MB90335 Series RETI ; Return from interrupt processing CODE ENDS ;-----Vector setting------------------------------------------------------------- VECT CSEG ABS=0FFH 00FFDCH WARI 00FFDCH ; Set reset vector START ; Set to single-chip mode...
  • Page 496: Chapter 22 Dual Operation Flash Memory

    22.4 How to Start Automatic Algorithm of Flash Memory 22.5 Reset Vector Addresses in Flash Memory 22.6 Check the Execution State of Automatic Algorithm 22.7 Details of Programming/Erasing Flash Memory 22.8 Operation of Dual Operation Flash Memory Code: CM44-00103-1E Page: 481, 484, 489 CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 497: Overview Of Dual Operation Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.1 Overview of Dual Operation Flash Memory 22.1 Overview of Dual Operation Flash Memory Dual Operation Flash Memory is allocated to FF bank in CPU memory map. The function of the flash memory interface circuit enables the read access from CPU and the program access.
  • Page 498 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.1 Overview of Dual Operation Flash Memory Note: The function of the manufacture code and device code to be read is not provided. These codes cannot be accessed by any command. ■ Programming and Erasing Flash Memory •...
  • Page 499: Sector/Bank Configuration Of Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.2 Sector/Bank Configuration of Flash Memory 22.2 Sector/Bank Configuration of Flash Memory This section explains the sector/bank configuration of flash memory. ■ Sector and Bank Configuration of Dual Operation Flash Memory Figure 22.2-1 shows the sector configuration of dual operation flash memory. The upper and lower addresses of each sector are given in the figure.
  • Page 500 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.2 Sector/Bank Configuration of Flash Memory Figure 22.2-1 Sector Configuration of Dual Operation Flash Memory Flash memory CPU address Writer address* FF0000 70000 SA0 (4 Kbytes) FF0FFF 70FFF FF1000 71000 SA1 (4 Kbytes)
  • Page 501: Registers Of Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory 22.3 Registers of Flash Memory This section explains the registers of flash memory. ■ List of Registers and Reset Values of Flash Memory Figure 22.3-1 List of Registers and Reset Values of Flash Memory ×...
  • Page 502: Flash Memory Control Status Register (Fmcs)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory 22.3.1 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS) controls the flash memory and shows the operating state of flash memory. ■ Flash Memory Control Status Register (FMCS) Figure 22.3-2 shows the register configuration of the flash memory control status register (FMCS).
  • Page 503 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory Table 22.3-1 Functions of Flash Memory Control Status Register (FMCS) Bit Name Function INTE: This bit enables or disables an interrupt as programming/erasing flash memory is Flash memory terminated.
  • Page 504 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory Note: The flash memory operation flag bit (RDYINT) and flash memory programming/erasing status bit (RDY) do not change simultaneously. A program should be created so as to identify the termination of programming/erasing using either the RDYINT bit or RDY bit.
  • Page 505: Flash Memory Write Control Register (Fwr0/Fwr1)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory 22.3.2 Flash Memory Write Control Register (FWR0/FWR1) The flash memory write control register (FWR0/FWR1) is a register in the flash memory interface, used to set the accidental write preventive function for the flash memory.
  • Page 506 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory Figure 22.3-4 Flash Memory Write-Protect, Write-Enable, Accidental-Write-Preventive Status Example in the Flash Memory Write Control Register (FWR0/FWR1) Register Register Initialize Initialize write write accidental- Write Write write-...
  • Page 507 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory Table 22.3-2 Functions of Flash Memory Write Control Register (FWR0/FWR1) Bit Name Function bit15 to Reserved: Reserved bits Always set these bits to "0". The reading value is irregular.
  • Page 508 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory ■ Flash Memory Write Control Register (FWR0/FWR1) Setting Flow Set the FMCS:WE bit, then set the bits for sectors to write to and the bits for sectors to be prevented from an accidental write in the flash memory write control register (FWR0/FWR1) to "1"...
  • Page 509 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory ■ Setting of FMCS:WE When writing the flash memory, after setting the FMCS:WE bit to "1" in order to be write-enabled, then set the flash memory write control register (FWR0/FWR1). In case of FMCS:WE is "0", writing is disabled even if the flash memory write control register (FWR0/FWR1) is write-enabled.
  • Page 510: Sector Switching Register (Ssr0)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory 22.3.3 Sector Switching Register (SSR0) The sector switching register (SSR0) specifies the sector switching between SA3 and SA9 for operation of Dual Operation Flash. ■ Sector Switching Register (SSR0) Figure 22.3-6 shows the configuration of the sector switching register (SSR0).
  • Page 511 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.3 Registers of Flash Memory ■ SEN0 Bit Access Sector Map Figure 22.3-7 shows the access sector map based on the SEN0 setting. Figure 22.3-7 The Access Sector Map Based on the SEN0 Setting...
  • Page 512: How To Start Automatic Algorithm Of Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.4 How to Start Automatic Algorithm of Flash Memory 22.4 How to Start Automatic Algorithm of Flash Memory There are four commands for starting the automatic algorithm of flash memory: read/ reset, write, chip erase and sector erase. The sector erase command controls suspension and resumption.
  • Page 513 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.4 How to Start Automatic Algorithm of Flash Memory ■ Notes on Command Issuance Pay attention to the following points when issuing commands in the command sequence table: • Write-enable each required sector before issuing the first command.
  • Page 514: Reset Vector Addresses In Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.5 Reset Vector Addresses in Flash Memory 22.5 Reset Vector Addresses in Flash Memory The flash memory products of this series use hardwired reset vectors. In CPU mode, any read access to addresses FFFFDC...
  • Page 515: Check The Execution State Of Automatic Algorithm

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.6 Check the Execution State of Automatic Algorithm 22.6 Check the Execution State of Automatic Algorithm Since the programming/erasing flow is controlled by the automatic algorithm, hardware sequence flag can check the internal operating state inside of flash memory.
  • Page 516 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.6 Check the Execution State of Automatic Algorithm ● Explanation of hardware sequence flag Table 22.6-2 lists the functions of the hardware sequence flag. Table 22.6-2 List of Hardware Sequence Flag Functions State Programming →...
  • Page 517: Data Polling Flag (Dq7)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.6 Check the Execution State of Automatic Algorithm 22.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is a hardware sequence flag which mainly used to notify that the automatic algorithm is executing or has been completed using the data polling function.
  • Page 518 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.6 Check the Execution State of Automatic Algorithm Note: Read access to the specified address while the automatic algorithm starts is ignored. Data reading can be enabled after "1" is set to data polling flag (DQ7). Data reading after the end of the automatic algorithm should be performed following read access after completion of data polling has been checked.
  • Page 519: Toggle Bit Flag (Dq6)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.6 Check the Execution State of Automatic Algorithm 22.6.2 Toggle Bit Flag (DQ6) The toggle bit flag is a hardware sequence flag used to notify that the automatic algorithm is being executed or in the end state using the toggle bit function.
  • Page 520: Timing Limit Over Flag (Dq5)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.6 Check the Execution State of Automatic Algorithm 22.6.3 Timing Limit Over Flag (DQ5) The timing limit over flag (DQ5) is a hardware sequence flag that notifies flash memory that the execution of the automatic algorithm has exceeded a prescribed time (the time required for programming/erasing).
  • Page 521: Sector Erase Timer Flag (Dq3)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.6 Check the Execution State of Automatic Algorithm 22.6.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag is used to notify during the period of waiting for sector erasing after the sector erase command has started.
  • Page 522: Details Of Programming/Erasing Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory 22.7 Details of Programming/Erasing Flash Memory This section explains the procedure for inputting commands starting the automatic algorithm, and for read/reset of flash memory, programming, chip erasing, sector erasing, sector erasing suspension and sector erasing resumption.
  • Page 523: Read/Reset State In Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory 22.7.1 Read/Reset State in Flash Memory This section explains the procedure for inputting the read/reset command to place flash memory in the read/reset state. ■ Read/Reset State in Flash Memory •...
  • Page 524: Data Programming To Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory 22.7.2 Data Programming to Flash Memory This section explains the procedure for inputting the program command to program data to flash memory. ■ Data Programming to Flash Memory •...
  • Page 525 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory Figure 22.7-1 Example of Data Programming Procedure Start FMCS: WE (bit5) Programming enabled FWR0/FWR1 Accidental write preventive function setting (Accidental write preventive sector: 0, writing sector...
  • Page 526: Data Erase From Flash Memory (Chip Erase)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory 22.7.3 Data Erase from Flash Memory (Chip Erase) This section explains the procedure for inputting the chip erase command to erase all data from flash memory.
  • Page 527: Erasing Any Data In Flash Memory (Sector Erasing)

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory 22.7.4 Erasing Any Data in Flash Memory (Sector Erasing) This section explains the procedure for inputting the sector erase command to erase any data in flash memory. Sector-by-sector erasing is enabled and multiple sectors can be specified at the same time.
  • Page 528 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory Figure 22.7-2 Example of Sector Erasing Procedure Start FMCS : WE (bit5) Erasing enabled FWR0/FWR1 Accidental write preventive function setting (Accidental write preventive sector: 0, writing sector...
  • Page 529: Sector Erase Suspension

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory 22.7.5 Sector Erase Suspension This section explains the procedure for inputting the sector erase suspend command to suspend sector erasing. Data can be read from the sector not being erased.
  • Page 530: Sector Erase Resumption

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.7 Details of Programming/Erasing Flash Memory 22.7.6 Sector Erase Resumption This section explains the procedure for inputting the sector erase resume command to resume erasing of the suspended flash memory sector. ■ Erase Resumption •...
  • Page 531: Operation Of Dual Operation Flash Memory

    CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.8 Operation of Dual Operation Flash Memory 22.8 Operation of Dual Operation Flash Memory Pay particular attention to the following points when using Dual Operation Flash: • Interrupt occurring when the upper bank is reprogrammed •...
  • Page 532 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.8 Operation of Dual Operation Flash Memory ■ Operation during Write/Erase • If the interrupt is generated during write/erase to flash memory, the write/erase operation to flash memory is prohibited in interrupt routine.
  • Page 533 CHAPTER 22 DUAL OPERATION FLASH MEMORY MB90335 Series 22.8 Operation of Dual Operation Flash Memory FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 534: Chapter 23 Example Of Connecting Serial Writing

    AF220/AF210/AF120/AF110 flash microcontroller programmer made by Yokogawa Digital Computer Corporation. 23.1 Basic Configuration 23.2 Oscillation Clock Frequency and Serial Clock Input Frequency 23.3 Flash Microcontroller Programmer System Configuration 23.4 Example of Connecting Serial Writing CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 535: Basic Configuration

    MB90335 Series 23.1 Basic Configuration The MB90F337 supports the serial on-board programming of flash ROM (Fujitsu standard). The specification for serial on-board programming are explained below. ■ The Serial On-Board Writing Basic Component The flash microcontroller programmer made by Yokogawa Digital Computer Corporation is used for Fujitsu standard serial on-board programming.
  • Page 536 CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING 23.1 Basic Configuration MB90335 Series ■ Pins Used for Fujitsu Standard Serial On-Board Programming Table 23.1-1 shows the function of pins used for Fujitsu standard serial on-board programming. Table 23.1-1 Function of Used Pins Function Supplementary Information...
  • Page 537: Oscillation Clock Frequency And Serial Clock Input Frequency

    CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING 23.2 Oscillation Clock Frequency and Serial Clock Input Frequency MB90335 Series 23.2 Oscillation Clock Frequency and Serial Clock Input Frequency The MB90F337 serial clock frequency that can be input is determined by the following...
  • Page 538: Flash Microcontroller Programmer System Configuration

    AZ221 RS232 C cable for PC/AT for writer AZ210 Standard target probe (a) length: 1 m FF201 Control module for Fujitsu F MC-16LX flash microcontroller AZ290 Remote controller 4 Mbytes PC Card (Option) flash memory capacity-512 Kbytes correspondence Contact: Yokogawa Digital Computer Corporation Tel: + 81-42-333-6224...
  • Page 539: Example Of Connecting Serial Writing

    CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING 23.4 Example of Connecting Serial Writing MB90335 Series 23.4 Example of Connecting Serial Writing The examples of serial write connection is shown below. ■ Example of Connecting Serial Writing Example of connecting serial writing has following two types.
  • Page 540: Example Connection In Single-Chip Mode (When Using User Power)

    CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING 23.4 Example of Connecting Serial Writing MB90335 Series 23.4.1 Example Connection in Single-chip Mode (when Using User Power) In a user system, from TAUX3 and TMODE of AF220/AF210/AF120/AF110, "1" for MD1 and "0" for MD0 are input to the MD2 and MD0 mode pins, which have been set to the single chip mode;...
  • Page 541 CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING 23.4 Example of Connecting Serial Writing MB90335 Series Notes: • When the SIN0, SOT0, or SCK0 pin is used also in a user system, the control circuit shown in Figure 23.1-2 is required like P60. (During serial write, the user circuit can be disconnected using the /TICS signal from the flash microcontroller programmer.)
  • Page 542: Example Of Minimum Connection To Flash Microcontroller Programmer (When Using User Power)

    CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING 23.4 Example of Connecting Serial Writing MB90335 Series 23.4.2 Example of Minimum Connection to Flash Microcontroller Programmer (when Using User Power) During serial write, when MD2, MD0, and P60 pins are set as shown in Figure 23.4-2, it is unnecessary to connect these pins with the flash microcontroller programmer.
  • Page 543 CHAPTER 23 EXAMPLE of CONNECTING SERIAL WRITING 23.4 Example of Connecting Serial Writing MB90335 Series Notes: • When the SIN0, SOT0, or SCK0 pin is used also in a user system, the control circuit shown in Figure 23.1-2 is required. (During serial write, the user circuit can be disconnected using the /TICS signal from the flash microcontroller programmer.)
  • Page 544: Appendix

    APPENDIX The appendix describes the memory map and the instructions used in the F MC-16LX. APPENDIX A Memory Map APPENDIX B Instructions CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 545: Appendix A Memory Map

    APPENDIX A Memory Map MB90335 Series APPENDIX A Memory Map The memory space divides into three modes. ■ Memory Map Figure A-1 Memory Map of MB90335 Series Single chip mode (with ROM mirror function) MB90V330A MB90F337 MB90337 FFFFFF FFFFFF FFFFFF...
  • Page 546 APPENDIX A Memory Map MB90335 Series Notes: • When the ROM mirror function register has been set, the mirror image data at higher addresses (FF8000 to FFFFFF ) of FF bank is visible from the higher addresses (008000 to 00FFFF ) of bank 00.
  • Page 547 APPENDIX A Memory Map MB90335 Series ■ I/O Map Table A-1 lists addresses assigned to registers of each peripheral function. Table A-1 I/O Map (1 / 8) Address Registers Abbreviation Access Release Initial value 000000 XXXXXXXX Port 0 data register...
  • Page 548 APPENDIX A Memory Map MB90335 Series Table A-1 I/O Map (2 / 8) Address Registers Abbreviation Access Release Initial value 000026 00100000 Serial mode register 1 SMR1 000027 00000100 Serial control register 1 SCR1 R/W,W UART1 Serial input data register 1/serial output data...
  • Page 549 APPENDIX A Memory Map MB90335 Series Table A-1 I/O Map (3 / 8) Address Registers Abbreviation Access Release Initial value 00005C 00000000 PWC Control Status Registers PWCSR R/W,R 00005D 0000000X 00005E 00000000 16-bit PWC timer PWC data buffer register PWCR...
  • Page 550 APPENDIX A Memory Map MB90335 Series Table A-1 I/O Map (4 / 8) Address Registers Abbreviation Access Release Initial value 0000A5 Use prohibited 0000A7 Watchdog 0000A8 X-XXX111 Watchdog timer control register WDTC R, W Timers Time-base 0000A9 1--00100 Time-base timer control register...
  • Page 551 APPENDIX A Memory Map MB90335 Series Table A-1 I/O Map (5 / 8) Address Registers Abbreviation Access Release Initial value 0000C0 00000000 Host control register 0 HCNT0 0000C1 00000001 Host control register 1 HCNT1 0000C2 00000000 Host interruption register HIRQ...
  • Page 552 APPENDIX A Memory Map MB90335 Series Table A-1 I/O Map (6 / 8) Address Registers Abbreviation Access Release Initial value 0000D2 01000000 EP0 control register EP0C 0000D3 XXXX0000 0000D4 00000000 EP1 control register EP1C 0000D5 01100001 0000D6 01000000 EP2 control register...
  • Page 553 APPENDIX A Memory Map MB90335 Series Table A-1 I/O Map (7 / 8) Address Registers Abbreviation Access Release Initial value 0000F4 XXXXXXXX EP2 data register EP2DT 0000F5 XXXXXXXX 0000F6 XXXXXXXX EP3 data register EP3DT 0000F7 XXXXXXXX USB function 0000F8 XXXXXXXX...
  • Page 554 APPENDIX A Memory Map MB90335 Series Table A-1 I/O Map (8 / 8) Address Registers Abbreviation Access Release Initial value 00790F Use prohibited 00791F 007920 XXXXXXXX DMA Buffer address pointer lower 8 bit DBAPL 007921 XXXXXXXX DMA Buffer address pointer middle 8 bit...
  • Page 555 APPENDIX A Memory Map MB90335 Series ■ Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers Table A-2 lists the correspondence between interrupt factors, and interrupt vectors and interrupt control registers. Table A-2 Correspondence between Interrupt Factors, and Interrupt Vectors and Interrupt Control...
  • Page 556 APPENDIX A Memory Map MB90335 Series : Available. With the EI OS stop function (the interrupt request flag is cleared with the interrupt clear signal. With a stop request.) ❍ : Available (the interrupt request flag is cleared with the interrupt clear signal.) Δ...
  • Page 557: Appendix B Instructions

    APPENDIX B Instructions MB90335 Series APPENDIX B Instructions APPENDIX B describes the instructions used by the F MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List...
  • Page 558: Instruction Types

    APPENDIX B Instructions B.1 Instruction Types MB90335 Series Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
  • Page 559: Addressing

    APPENDIX B Instructions B.2 Addressing MB90335 Series Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
  • Page 560 APPENDIX B Instructions B.2 Addressing MB90335 Series ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to the...
  • Page 561: Direct Addressing

    APPENDIX B Instructions B.3 Direct Addressing MB90335 Series Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.)
  • Page 562 APPENDIX B Instructions B.3 Direct Addressing MB90335 Series Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general- purpose register R0.) Before execution A 0 7 1 6...
  • Page 563 APPENDIX B Instructions B.3 Direct Addressing MB90335 Series ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
  • Page 564 APPENDIX B Instructions B.3 Direct Addressing MB90335 Series ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
  • Page 565 APPENDIX B Instructions B.3 Direct Addressing MB90335 Series ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 to 0000FF explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
  • Page 566 APPENDIX B Instructions B.3 Direct Addressing MB90335 Series ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
  • Page 567: Indirect Addressing

    APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to...
  • Page 568 APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.)
  • Page 569 APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi.
  • Page 570 APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general- purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
  • Page 571 APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
  • Page 572 APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series Figure B.4-9 Example of Register List (rlst) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E ×...
  • Page 573 APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB).
  • Page 574 APPENDIX B Instructions B.4 Indirect Addressing MB90335 Series ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.)
  • Page 575: Execution Cycle Count

    APPENDIX B Instructions B.5 Execution Cycle Count MB90335 Series Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch.
  • Page 576 APPENDIX B Instructions B.5 Execution Cycle Count MB90335 Series ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode...
  • Page 577 APPENDIX B Instructions B.5 Execution Cycle Count MB90335 Series Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register...
  • Page 578: Effective Address Field

    APPENDIX B Instructions B.6 Effective address field MB90335 Series Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Byte count of extended Code Representation Address format address part (RL0) Register direct: Individual parts correspond to...
  • Page 579: How To Read The Instruction List

    APPENDIX B Instructions B.7 How to Read the Instruction List MB90335 Series How to Read the Instruction List Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list.
  • Page 580 APPENDIX B Instructions B.7 How to Read the Instruction List MB90335 Series Table B.7-1 Description of Items in the Instruction List (1/2) Item Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry).
  • Page 581 APPENDIX B Instructions B.7 How to Read the Instruction List MB90335 Series Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol Explanation R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7...
  • Page 582: F 2 Mc-16Lx Instruction List

    APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F MC-16LX. ■ F MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic Operation byte (A) ← (dir) A,dir byte (A) ←...
  • Page 583 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic Operation word (A) ← (dir) MOVW A,dir word (A) ← (addr16) MOVW A,addr16 word (A) ← (SP) MOVW A,SP word (A) ← (RWi)
  • Page 584 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← (A) + imm8 A,#imm8 byte (A) ← (A) + (dir) A,dir byte (A) ← (A) + (ear) A,ear byte (A) ←...
  • Page 585 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic Operation byte (ear) ← (ear) + 1 2 × (b) byte (eam) ← (eam) + 1 5+(a) byte (ear) ← (ear) - 1 2 ×...
  • Page 586 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) DIVU A,ear word (A) / byte (ear) quotient →...
  • Page 587 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) A,ear word (A) / byte (ear) quotient →...
  • Page 588 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic Operation byte (A) ← (A) and imm8 A,#imm8 byte (A) ← (A) and (ear) A,ear byte (A) ← (A) and (eam)
  • Page 589 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic Operation long (A) ← (A) and (ear) ANDL A,ear long (A) ← (A) and (eam) ANDL A,eam 7+(a) long (A) ← (A) or (ear) A,ear long (A) ←...
  • Page 590 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← Right rotation with carry RORC byte (A) ← Right rotation with carry ROLC byte (ear) ← Right rotation with carry RORC 2 ×...
  • Page 591 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-13 31 Branch 1 Instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/ Branch on (Z) = 0 BC/BLO rel Branch on (C) = 1 BNC/ Branch on (C) = 0...
  • Page 592 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-14 19 Branch 2 Instructions Mnemonic Operation S T N Z V C CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16...
  • Page 593 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic Operation word (SP) ← (SP) - 2, ((SP)) ← (A) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (AH) PUSHW word (SP) ←...
  • Page 594 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-16 21 Bit Operand Instructions Mnemonic Operation byte (A) ← (dir:bp)b MOVB A,dir:bp byte (A) ← (addr16:bp)b MOVB A,addr16:bp byte (A) ← (io:bp)b MOVB A,io:bp 2 × (b) bit (dir:bp)b ← (A)
  • Page 595 APPENDIX B Instructions B.8 F MC-16LX Instruction List MB90335 Series Table B.8-18 10 String Instructions Mnemonic Operation byte transfer @AH+ ← @AL+, counter = RW0 MOVS / MOVSI byte transfer @AH- ← @AL-, counter = RW0 MOVSD byte search @AH+ ← AL, counter = RW0 SCEQ / SCEQI byte search @AH- ←...
  • Page 596: Instruction Map

    APPENDIX B Instructions B.9 Instruction Map MB90335 Series Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F MC-16LX instruction map.
  • Page 597 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction . . . Byte 1 Byte 2 Operand...
  • Page 598 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-2 Basic Page Map CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 599 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-3 Bit Operation Instruction Map (First Byte = 6C FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 600 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-4 Character String Operation Instruction Map (First Byte = 6E CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 601 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-5 2-byte Instruction Map (First Byte = 6F FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 602 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-6 ea Instruction 1 (First Byte = 70 CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 603 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-7 ea Instruction 2 (First Byte = 71 FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 604 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-8 ea Instruction 3 (First Byte = 72 CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 605 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-9 ea Instruction 4 (First Byte = 73 FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 606 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-10 ea Instruction 5 (First Byte = 74 CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 607 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-11 ea Instruction 6 (First Byte = 75 FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 608 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-12 ea Instruction 7 (First Byte = 76 CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 609 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-13 ea Instruction 8 (First Byte = 77 FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 610 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-14 ea Instruction 9 (First Byte = 78 CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 611 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79 FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 612 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-16 MOV Ri, ea Instruction (First Byte = 7A CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 613 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7B FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 614 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-18 MOV ea, Ri Instruction (First Byte = 7C CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 615 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7D FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 616 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-20 XCH Ri, ea Instruction (First Byte = 7E CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED...
  • Page 617 APPENDIX B Instructions B.9 Instruction Map MB90335 Series Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7F FUJITSU MICROELECTRONICS LIMITED CM44-10137-6E...
  • Page 618: Index

    INDEX The index follows on the next page. This is listed in alphabetic order.
  • Page 619 Index Numerics 16-bit Reload Register ....... 328 ..........31 16-bit Reload Register 0 (TMRLR0) Accumulator (A) 16-bit Timer Register 0 (TMR0)/16-bit Reload Register 0 Access Area ........... 327 (TMRLR0) Relation between Access Area and Physical Address 16-bit Reload Timer ............161 ....
  • Page 620 Block Diagram of PWC Timer ..........125 Block Diagram of ROM Mirror Function Select Module Clock Supply Map ............456 ......7 Block Diagram of the MB90335 Series .......41 Common Register Bank Prefix (CMR) ......172 Block Diagram of Time-base Timer Command Issuance ........
  • Page 621 Connection Status Disconnection Status, Connection Status of the External Port Direction Register (DDR0 to DDR2,DDR4 to DDR6) .......... 271 ............167 USB Device Continuous Measurement DDWR Single Measurement and Continuous Measurement Configuration of DMA Descriptor Window Register ............310 ..........94 (DDWR) Control Circuit Dedicated Baud Rate...
  • Page 622 .....364 DIVR Operation Process of DTP/External Interrupt ......358 Overview of DTP/External Interrupt PWC Ratio of Dividing Frequency Control Register (DIVR) ....359 ............299 Register List of DTP/External Interrupt DTP/Interruption Factor register DMA Buffer Address Pointer DTP/Interruption Factor Register (EIRR: External Interrupt DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) ........360 ............
  • Page 623 ..369 EP0 Control Register List of Register in Extended I/O Serial Interface ....368 ......... 202 Outline of Extended I/O Serial Interface EP0 Control Register (EP0C) Outline of Operation of Extended I/O Serial Interface EP0 to EP5 Data Register ............
  • Page 624 FRAME Setting Register Host ..... 267 FRAME Setting Register (HFRAME) ..........236 Wake-up from Host Fujitsu Standard Host Address Register Pins Used for Fujitsu Standard Serial On-Board ......265 ........515 Host Address Register (HADR) Programming Host Control Register Function .....250 ......51...
  • Page 625 HTOKEN Initial Value ....268 ..38 Host Token Endpoint Register (HTOKEN) Direct Page Register (DPR)<Initial Value: 01 > ..... 355 Initial Value of Hardware Component Initial Values List of Registers and Initial Values of Address Match I/O Area ......... 462 Detection Function .............
  • Page 626 Count Clock and Maximum Cycle Interrupt Vector Interrupt Factors, Interrupt Vectors, and Interrupt Control MB90335 Series ..........534 Registers ......7 Block Diagram of the MB90335 Series ............ 49 Interrupt Vector ........2 Feature of MB90335 Series Interruption Interruption Function of Extended I/O Serial Interface .......159...
  • Page 627 Minimum Operating State ........312 ......... 306 Minimum Input Pulse Width Check Operating State ........470 Setting and Operating State Minimum Connection Operation Example of Minimum Connection to Flash Microcomputer ..521 Programmer (when Using User Power) Each Register Operation when Write Command Responds ............
  • Page 628 ..... 341 Block Diagram of 8/16-bit PPG Timer ......428 Example of UART Programming ......355 Interrupts of 8/16-bit PPG Timer Pins Used for Fujitsu Standard Serial On-Board ....352 Outline of Operation of 8/16-bit PPG Timer ........515 Programming ....340 Overview of 8/16-bit Timer PPG Timer ....477...
  • Page 629 Programming Procedure Register ........ 503 ..38 Data Programming Procedure Direct Page Register (DPR)<Initial Value: 01 > Each Register Operation when Read Command Responds ............229 ..........33 Processor Status (PS) ........ 202 EP0 Control Register (EP0C) Pulse ... 223 EP0 to EP5 Data Register (EP0DT to EP5DT) ........
  • Page 630 ROM Mirror Function Select Register (ROMM) ....395 Serial Mode Register 0,1 (SMR0,SMR1) Serial On-Board ........34 Register Bank Pointer (RP) Pins Used for Fujitsu Standard Serial On-Board ........515 Programming ..514 The Serial On-Board Writing Basic Component Serial Output Data Register Serial Output Data Register 0,1 (SODR0,SODR1) ....
  • Page 631 SIDR Start ... 400 Serial Input Data Register 0,1 (SIDR0,SIDR1) Start/stop Timing of Shift Operation and Timing of I/O ............381 Single Measurement Start Condition Single Measurement and Continuous Measurement ............310 ........... 447 Start Condition Single Shot Mode Startup ....
  • Page 632 Transfer Serial Data Operation of Interval Timer Function (Time-base Timer) ............177 ......382 Operation during Transfer Serial Data ......180 Operations of Time-base Timer Transfer Speed ....179 Precautions when Using Time-base Timer Acquiring Transfer Speed of Destination USB Device and ....
  • Page 633 UTRLR Acquiring Transfer Speed of Destination USB Device and UART Prescaler Control Register 0, 1 (UTCR0, UTCR1) ........271 Selecting Clock and UART Prescaler Reload Register 0, 1 .... 37 ......402 Bank Registers (PCB, DTB, USB, SSB, ADB) (UTRLR0, UTRLR1) ......
  • Page 634 CM44-10137-6E FUJITSU MICROELECTRONICS • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90335 Series HARDWARE MANUAL August 2009 the sixth edition FUJITSU MICROELECTRONICS LIMITED Published Sales Promotion Dept. Edited...

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