Dmac Ch0 To Ch4 Control/Status Registers B - Fujitsu FR60 Hardware Manual

CHAPTER 16 DMA CONTROLLER (DMAC)
16.2.2

DMAC ch0 to ch4 Control/Status Registers B

The DMACB0 to 4 registers control the operation of the DMAC channels. A separate
register is provided for each channel.
■ Functions of the DMACB0 to 4 Bits
The functions of the DMACB0 to 4 bits are shown below.
bit 31
TYPE [1 : 0]
bit 15
[Bits 31 to 30] TYPE (TYPE): Transfer type setting
These bits specify the operation type of the corresponding channel as described below.
2-cycle transfer mode:
In this mode, the transfer source address (DMASA) and transfer destination address (DMADA) are set
and transfer is performed by repeating the read operation and write operation for the number of times
specified by the transfer count. All areas can be specified as a transfer source or transfer destination (32-
bit ADDRESS).
Fly-by transfer mode:
In this mode, external ↔ external transfer is performed in one cycle by setting a memory address as the
transfer destination address (DMADA). Be sure to specify an external area for the memory address.
TYPE
• When reset: Initialized to "00".
• These bits are readable and writable.
*: The MB91F353A/351A/352A/353A do not support fly-by transfer. Setting of the TYP bit to "01" or
"10" is not allowed.
482
30 29 28 27
MOD [1 : 0] WS [1 : 0]
14 13 11 11
SASZ [7 : 0]
00 2-cycle transfer (initial value)
01 Fly-by: Memory to I/O transfer
10 Fly-by: I/O to memory transfer
11 Setting disabled
26 25 24 23
SADM DADM DTCR SADR DADR ERIE EDIE
10 9 8 7
(Initial value: 00000000_00000000_XXXXXXXX_XXXXXXXX
Function
22 21 20 19
6 5 4 3
DASZ [7 : 0]
18 17 16
DSS[2 : 0]
2 1 0
)
B