Fujitsu FR60 Hardware Manual page 168

CHAPTER 3 CPU AND CONTROL UNITS
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Main clock oscillation stabilization wait timer
The main clock oscillation stabilization wait timer is a 32-bit incremental counter that uses the main clock
source oscillation as the count clock.
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Counter clear circuit
The counter clear circuit clears the counter not only when the WCL bit of the OSCR register is set to "0"
but also when a reset (INIT) request is generated.
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Interval timer selector
The interval timer selector selects one of the three frequency-divide outputs of the main clock oscillation
stabilization wait timer counter for the interval timer. The trailing edge of the selected frequency-divide
output becomes an interrupt source.
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Main clock oscillation stabilization wait timer control register (OSCR)
The main clock oscillation stabilization wait timer control register is used to select the interval time, clear
the counter, control interrupts, and check counter status.
■ Explanation of the Main Clock Oscillation Stabilization Wait Timer Register
The configuration of the main clock oscillation stabilization wait timer register is shown below:
OSCR
bit
00000490
H
[Bit 15] WIF (timer interrupt flag)
This bit is the main clock oscillation stabilization wait interrupt request flag.
This bit is set to "1" at the trailing edge of the selected divided output for the interval timer.
If this bit and the interrupt request enable bit are "1", a main clock oscillation stabilization wait timer
interrupt request is outputted.
Value
0
1
• This bit is cleared to "0" by a reset (INIT) request.
• Data can be written to and read from this bit. However, only "0" can be written. If an attempt is made to
write "1" to this bit, its value is not changed.
• If a read modify write instruction is issued, "1" is always read from this bit.
150
15 14 13 12
WIF WIE WEN
R/W R/W R/W
Main clock oscillation stabilization wait timer interrupt not requested (default value)
Main clock oscillation stabilization wait timer interrupt requested
11 10 9
- - WS1 WS0
R/W R/W
Explanation
Initial value
8
at INIT at RST
00 xx
WCL
H H
W
Access
R/W