Fujitsu FR60 Hardware Manual page 413

■ Serial Status Register (SSR)
The bit configuration of the serial status register (SSR) is shown below.
Note: The MB91F353A/351A/352A/353A do not have SSR ch4.
SSR
Address : ch0 000060
ch1 000068
ch2 000070
ch3 0000C0
ch4 0000C8
The SSR is configured from flags that indicate the operating status of the UART.
[Bit 7] PE (Parity Error)
This bit, which is an interrupt request flag, is set when a parity error occurs during reception.
To clear the flag when it has been set, write "0" to the REC bit (Bit 10) of the SCR register.
If the PE bit is set, the SIDR data becomes invalid.
Value
[Bit 6] ORE (Over Run Error)
This bit, which is an interrupt request flag, is set when an overrun error occurs during reception.
To clear the flag when it has been set, write "0" to the REC bit of the SCR register.
If the ORE bit is set, the SIDR data becomes invalid.
Value
7 6 5
H
H PE ORE FRE
H R R R
H
H
0 No parity error has occurred. [initial value]
1 A parity error has occurred.
0 No overrun error has occurred. [initial value]
1 An overrun error has occurred.
4 3 2
RDRF TDRE BDS
R R R/W R/W
Meaning
Meaning
1 0 Initial value
00001000
RIE TIE
R/W
B
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