Fujitsu FR60 Hardware Manual page 660

INDEX
Suppressing
Suppressing DMA ............................................ 506
Switching
Wait Time after Switching From the Subclock to the
Main Clock......................................... 107
Switching Shared Port
Switching Shared Port Functions ......................... 35
Synchronization
Asynchronous (Start-stop Synchronization)
Mode ................................................. 400
Synchronous
Normal and Synchronous Standby Operations
.......................................................... 142
Synchronous Reset Operation............................ 102
Synchronous Write Enable Output Timing
Synchronous Write Enable Output Timing
(TYP[3:0]=0000
SYSCLK
MCLK and SYSCLK.......................................... 33
System Condition Code Register
SCR (System Condition Code Register) ............... 60
System Configuration
System Configuration of the Flash Microcontroller
Programmer ........................................ 572
System Construction
Example of System Construction
(Using Mode 1)................................... 407
System Stack Pointer
SSP (System Stack Pointer)................................. 62
System Stack Pointer (SSP)................................. 77
T
Table Base Register
Table Base Register (TBR).................................. 79
TBR (Table Base Register).................................. 61
TBCR
Timebase Counter Control Register (TBCR) ....... 117
TBR
Table Base Register (TBR).................................. 79
TBR (Table Base Register).................................. 61
TCCS
Timer Control Status Register (TCCS) ............... 281
TCDT
Timer Data Register (TCDT)............................. 280
TCR
Configuration of the Terminal and Timing Control
Register (TCR).................................... 184
Temporarily Stop Erase
Temporarily Stop Erase .................................... 551
Temporarily Stopping Sector Erase
Temporarily Stopping Sector Erase in Flash
Memory ............................................. 564
642
) .......... 210
,AWR=0000
B H
Temporary Stop
Starting from a Temporary Stop ........................ 508
Temporary Stopping
Optional Clear and Temporary Stopping of a Prefetch
Access ............................................... 219
Setting of Temporary Stopping by Writing to the
Control Register (Set Independently for Each
Channel or all Channels
Simultaneously) .................................. 511
Terminal and Timing Control Register
Configuration of the Terminal and Timing Control
Register (TCR) ................................... 184
Time Division I/O Interface
Control Signals on the Time Division I/O
Interface............................................. 189
Time Interval
Time Intervals for Main Clock Oscillation
Stabilization Wait Timer...................... 149
Timebase Counter
Timebase Counter ............................................ 129
Timebase Counter Clear Register
Timebase Counter Clear Register (CTBR).......... 119
Timebase Counter Control Register
Timebase Counter Control Register (TBCR) ...... 117
Timer
Block Diagram of the 8/16-bit Up/Down
Counters/Timers (ch0)......................... 250
Characteristics of the 8/16-bit Up/Down
Counters/Timers ................................. 247
List of Registers of the 8/16-bit Up/Down
Counters/Timers ................................. 248
Other Interval Timers and Counters ....................... 4
Overview of the 8/16-bit Up/Down
Counters/Timers ................................. 246
Various Timers .................................................... 3
Timer Control Status Register
Timer Control Status Register (TCCS) ............... 281
Timer Data Register
Timer Data Register (TCDT) ............................ 280
Timing
Timing for Clearing Interrupts During DMA ...... 510
Timing of 16-bit Free-running Timer Counting
......................................................... 285
Timing of 16-bit Output Compare Operation ...... 438
Timing of Clearing of the 16-bit Free-running
Timer................................................. 285
Timing of DACK Pin Output ............................ 520
Timing of DREQx Pin Input ............................. 530
Timing of the DEOP Pin Output........................ 520
Timing of the DREQ Pin Input for Continuing
Transfer Over the Same Channel .......... 520
Timing of the DSTP Pin Input........................... 520
Timing Chart
Interrupt Sources and Timing Chart ................... 318