Fujitsu FR60 Hardware Manual page 220

CHAPTER 4 EXTERNAL BUS INTERFACE
■ Halfword Access
External access using halfword access is shown below:
16-bit bus
width
Internal
D31
D00
D31
D00
8-bit bus
width
D31
D00
Internal
D31
D00
202
Big endian mode
External
Reg terminal
address: "0"
D31
AA
BB
D16
AA
BB
(1)
Internal External
Reg terminal
address: "2"
D31
CC
DD
D16
CC
DD
(1)
Internal External
Reg terminal
address: "0" "1"
D31
AA BB
D24
AA
BB
D00
(1) (2)
External
Reg terminal
address: "2" "3"
D31
CC DD
D24
CC
DD
D00
(1) (2)
Control Internal
Reg
terminal
address: "0"
D31
WR0
WR1
AA
BB
D00
Control Internal
terminal Reg
address: "2"
D31
WR0
WR1
CC
DD
D00
Control
Internal
terminal Reg
address: "0" "1"
D31
WR0
AA
BB
D00
Control
Internal
terminal
Reg
address: "2" "3"
D31
WR0
CC
DD
D00
Little endian mode
External Control
terminal terminal
D31
WR0
BB
AA
D16
(1)
External Control
terminal terminal
D31
WR0
DD
WR1
CC
D16
(1)
External Control
terminal terminal
D31
WR0
BB AA
D24
D00
(1) (2)
External Control
terminal terminal
D31
WR0
CC DD
D24
D00
(1) (2)
WR1