Fujitsu FR60 Hardware Manual page 445

■ Input Capture Block Diagram
Figure 14.3-1 shows a block diagram of the input capture module.
Figure 14.3-1 Input Capture Block Diagram
16-bit timer count value (T15 to T00)
Capture data register
ch(0,2)
16-bit timer count value (T15 to T00)
Capture data register
ch(1,3)
Edge
detection
EG11 EG10 EG01
EG31 EG30 EG21
Edge
detection
ICP1 ICP0 IEC1 IEC0
ICP3 ICP2 IEC3 IEC2
IN0, 2
Input pin
EG00
EG20
IN1, 3
Input pin
Interrupt
Interrupt
427