Fujitsu FR60 Hardware Manual page 436

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
■ DMAC Interrupt Source Clear Register (SRCL)
The bit configuration of the DMAC interrupt source clear register (SRCL) is shown below.
This register must be accessed in byte units.
SRCL
Address : 000039
00003A
00003B
The DMAC interrupt source clear register is used to clear the SIO interrupt source. If an arbitrary value
is written to this register, the source of an interrupt to the DMAC is cleared. This register must be
accessed in byte units.
After a DMAC interrupt is generated, the DMAC interrupt source is retained until DMAC transfer ends
and the DMAC clears the DMAC interrupt source.
In interrupt processing that does not activate the DMAC, the DMAC interrupt source is retained even
though the serial I/O interrupt request flag has been cleared.
For this reason, if the SIO is specified as the DMAC activation source and the DMAC operation is
enabled with the DMAC interrupt source retained, the DMAC will be activated even though the serial I/
O interrupt request flag is not set. The result will be unexpected operation.
To avoid this error, use this register to clear the DMAC interrupt source before activating the DMAC.
In particular, be sure to clear the DMAC interrupt source specially if the DMAC is to be activated for
the first time or if the SIO has operated for an interrupt without the DMAC having been activated. (This
register is write-only.)
Note:
The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000039
invalid.)
418
7 6 5
- - -
H
R/W R/W R/W
H
H
4 3 2
- - -
R/W R/W R/W R/W
1 0
- - Initial value: --------
R/W
(undefined)
in the SRCL register is
H
B