Interrupt Control Register (Icr) - Fujitsu FR60 Hardware Manual

9.2.1

Interrupt Control Register (ICR)

An interrupt control register (ICR) is provided for each of the interrupt input and sets the
interrupt level of the corresponding interrupt request.
■ Bit Configuration of the Interrupt Control Register (ICR)
The bit configuration of the interrupt control register (ICR) is shown below.
bit
[Bits 4 to 0] ICR4 to 0
These bits, which are the interrupt level setting bits, specify the interrupt level of the corresponding
interrupt request.
If an interrupt request has an interrupt level defined in this register that exceeds the level mask value
defined in the ILM register of the CPU, it is masked by the CPU.
These bits are initialized to 11111
Table 9.2-1 shows the correspondence between possible interrupt level setting bits and interrupt levels.
7 6 5 4
- - - ICR4
R
3 2 1
ICR3 ICR2 ICR1
R/W R/W R/W
by a reset.
B
0 Initial value
---11111
ICR0
R/W
329