Fujitsu FR60 Hardware Manual page 224

CHAPTER 4 EXTERNAL BUS INTERFACE
■ Read → Write Timing (TYP[3:0]=0000
Figure 4.5-2 shows the read → write timing.
MCLK
A[23:0]
AS
CSn
RD
WRn
D[31:16]
• Setting of the W07/W06 bits of the AWR register enables [0:3] idle cycles to be inserted.
• Settings in the CS area on the read side are enabled.
• This idle cycle is inserted if the next access after a read access is write access or access to another area.
206
,AWR=0048
B
Figure 4.5-2 Read → Write Timing
Read Idle
)
H
Write