Fujitsu FR60 Hardware Manual page 435

■ Serial I/O Prescaler Control Register (CDCR)
The bit configuration of the serial I/O prescaler control register (CDCR) is shown below.
This register must be accessed in byte units.
CDCR
Address : 000032
000034
000036
Note:
The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000032
invalid.)
[Bit 15] Machine clock divide mode select (MD)
The machine clock divide mode select bit is the operation enable bit of the communication prescaler.
Value
[Bits 11 to 8] Divide 3 to divide 0 (DIV3 to DIV0)
The divide 3 to divide 0 bits are used to specify the division ratio for the peripheral system clock
(CLKP).
Note:
If the division ratio is changed, wait before starting communication until the time equal to the two
divided clock pulses has elapsed for clock stabilization.
15 14 13
MD - -
H
R/W - -
H
H
0 Communication prescaler operation is disabled. (Default)
1 Communication prescaler operation is enabled.
DIV3 to 0
1101B
1100B
1011B
1010B
1001B
1000B
12 11 10
- DIV3 DIV2 DIV1
- R/W R/W R/W
Meaning
Division ratio
3
4
5
6
7
8
9 8
DIV0 Initial value: 0---1111
R/W
in the CDCR is
H
B
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