Fujitsu FR60 Hardware Manual page 92

CHAPTER 3 CPU AND CONTROL UNITS
■ I Flag
A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as Bit 4 of the PS
register.
Value
0
1
■ Interrupt Level Mask (ILM) Register
A PS register (Bits 20 to 16) that holds an interrupt level mask value.
The CPU accepts only an interrupt request sent to it with an interrupt level higher than the level indicated
by the ILM.
The highest level is 0 (00000
Values that can be set by a program have a limit. If the original value is between 16 and 31, the new value
must be between 16 and 31. If an instruction that sets a value between 0 and 15 is executed, the specified
value plus 16 is transferred.
If the original value is between 0 and 15, any value between 0 and 31 may be set. Use the STILM
instruction to specify an arbitrary value.
■ Level Mask for Interrupt and NMI
If an NMI or interrupt request occurs, the interrupt level (Table 3.7-1 ) of the interrupt source is compared
with the level mask value held in the ILM. A request meeting the following condition is masked and is not
accepted:
Interrupt level of cause ≥ Level mask value
74
Interrupts prohibited
Cleared to "0" if the INT instruction is executed.
(Note that a value saved on the stack is the value before it is cleared.)
Interrupts permitted
The mask processing of an interrupt request is controlled by the value in the ILM
register.
) and the lowest level is 31 (11111
B
Description
).
B