Fujitsu FR60 Hardware Manual page 467

[Bit 14] BEIE (Bus Error Interrupt Enable)
This bit is the bus error interrupt enable bit.
Value
0
1
An interrupt occurs if this bit is set to "1" and the BER bit is set to "1".
[Bit 13] SCC (Start Condition Continue)
This bit is the repeated [START] condition generation bit.
During writing
Value
0
1
The read value of this bit is always "0".
If "1" is written to this bit in master mode (MSS = 1, INT = 1), a repeated START condition is generated
and the INT bit is automatically cleared.
[Bit 12] MSS (Master Slave Select)
This bit is the master or slave selection bit.
Value
0
1
• This bit is cleared when arbitration lost occurs during master transmission, causing slave mode to
start.
• Write "0" to this bit during setting a master interrupt flag (MSS=1, INT=1) to automatically clear the
INT bit. Then, generate a [STOP] condition to end the transfer.
Note:
The MSS bit functions as a direct reset. To detect a STOP condition, check the BB bit of the IBSR
register.
• If "1" is written to this bit while the bus is idle (MSS = 0, BB = 0), a START condition is generated
and the value of IDAR is sent.
• If "1" is written to this bit while the bus is busy (BB = 1, TRX = 0, MSS = 0), the I
transmission when the bus becomes idle. If the I
is accompanied by a write access during this time, the bus becomes idle after the transfer ends. If the
interface is transmitting as a slave (IBCR AAS = 1, TRX = 1) during this time, no data is sent even if
449
Bus error interrupt disabled
Bus error interrupt enabled
Has no meaning.
Generates a repeated START condition in master transfer.
Selects slave mode.
Selects master mode. Generates a START condition to enable the value
of the IDAR register to be sent as a slave address.
15.2 I
Function
Function
Function
2
C interface is specified as the address for a slave that
2
C Interface Register
2
C interface starts