Fujitsu FR60 Hardware Manual page 643

List of Registers of the 8/16-bit Up/Down
Counters/Timers ................................. 248
Operating States of the Counter ......................... 295
Other Interval Timers and Counters ....................... 4
Overview of the 8/16-bit Up/Down
Counters/Timers ................................. 246
PC (Program Counter) ........................................ 61
Counter Control Register
Counter Control Register High/Low ch0
(CCR H/L ch0) ................................... 252
Counter Control Register High/Low ch1
(CCR H/L ch1) ................................... 256
Counter Status Register
Counter Status Register 0/1 (CSR0/1) ................ 256
CPU
Configuration of the Flash Control/Status Register
(FLCR) (CPU Mode)........................... 540
CPU.................................................................. 52
CPU Clock (CLKB) ......................................... 108
FR CPU Features ................................................. 2
FR-CPU Programming Mode
(16 Bits,Read/Write Enabled)............... 546
FR-CPU ROM Mode (32 Bits,Read only) .......... 545
Pin States in Each CPU State ............................ 598
CS
CS -> RD/WR Setup
(TYP[3:0] =0101
CS Delay Setting
(TYP[3:0]=0000
Setting of CS -> RD/WR Setup and of RD/WR -> CS
Hold (TYP[3:0]=0000
.......................................................... 212
CSER
Configuration of the Chip Select Enable Register
(CSER) .............................................. 183
CSR
Counter Status Register 0/1 (CSR0/1) ................ 256
CTBR
Timebase Counter Clear Register (CTBR).......... 119
D
D/A Control Register
DACR0 (D/A Control Register 0)...................... 383
DACR1 (D/A Control Register 1)...................... 383
DACR2 (D/A Control Register 2)...................... 383
D/A Converter
D/A Converter ..................................................... 4
Features of the 8-bit D/A Converter ................... 380
D/A Converter Output Voltage
Logical Expressions for D/A Converter Output
Voltage .............................................. 384
D/A Data Register
DADR0 (D/A Data Register 0).......................... 382
DADR1 (D/A Data Register 1).......................... 382
, AWR=100B ) ....... 217
B H
) ........ 211
, AWR=000C
B H
,AWR=000B )
B H
DADR2 (D/A Data Register 2) ..........................382
DACK
FR30 Compatible Mode of DACK .....................532
Timing of DACK Pin Output .............................520
DACR
DACR0 (D/A Control Register 0) ......................383
DACR1 (D/A Control Register 1) ......................383
DACR2 (D/A Control Register 2) ......................383
DADR
DADR1 (D/A Data Register 1) ..........................382
DADR2 (D/A Data Register 2) ..........................382
DADR0
DADR0 (D/A Data Register 0) ..........................382
Data Direction Register
Data Direction Registers (DDR).........................235
Data Internal RAM/Instruction
Block Diagram of the Data Internal RAM/
Instruction Internal RAM Access Restriction
Functions ............................................576
Data Internal RAM/Instruction Internal RAM Access
Restriction
Data Internal RAM/Instruction Internal RAM Access
Restriction Function Registe .................576
Data Internal RAM/Instruction Internal RAM Access
Restriction
Operation of the Data Internal RAM/
Instruction Internal RAM Access Restriction
Functions ............................................579
Data RAM Limit Control Register
DRLR: Data RAM Limit Control Register
(D-Bus RAM Limit Control Register)
..........................................................577
Data Register
Data Register (IDAR) .......................................462
Overview of the Data Registers
(ADTHx and ADTLx)..........................375
Data Transfer
Example of Slave Address and Data Transfer
..........................................................468
D-bus
D-bus Memory ...................................................34
D-Bus RAM Limit Control Register
DRLR: Data RAM Limit Control Register
(D-Bus RAM Limit Control Register)
..........................................................577
DDR
Data Direction Registers (DDR).........................235
Debugger
Emulator and Monitor Debuggers ........................43
Precautions on the Debuggers ..............................36
Simulator Debugger ............................................43
Delay Slot
Branch Instructions with Delay Slot .....................68
Instructions not Using a Delay Slot ......................71
INDEX
625