Fujitsu FR60 Hardware Manual page 323

[Bit 8] (Unused bit)
[Bits 7 and 6] EGS1 and EGS0 (Trigger Input Edge Select Bit)
These bits are used to select an effective edge for the activation cause selected in general control
register 1.
Regardless of the mode that is selected, writing "1" to the bit of a software trigger enables the software
trigger.
EGS1 EGS0
0 0
0 1
1 0
1 1
[Bit 5] IREN (PPG Interrupt Request Enable)
Value
0 Disabled (initial value)
1 Enabled
[Bit 4] IRQF (PPG Interrupt Request Flag)
If bit 5, IREN, is enabled and an interrupt source selected in bits 3 and 2, the IRS1 and IRS0, occurs
then this bit is set and an interrupt request is generated and issued to the CPU.
This bit is cleared if "0" is written to it.
This bit remains unchanged if "1" is written to it.
The read value by a read-modify-write instruction is always "1", regardless of the bit value.
[Bits 3 and 2] IRS1, IRS0 (Interrupt Source Select)
These bits are used to select a source that sets bit 4, the IRQF.
IRS1 IRS0
0 0
0 1
1 0
1 1
[Bit 1] (reserved)
This bit is unused.
Not effective (initial value)
Rising edge
Falling edge
Both edges
Meaning
Interrupt source
Software trigger or trigger input (initial value)
Occurrence of a counter borrow (cycle match)
Occurrence of a duty match
Occurrence of a counter borrow (cycle match) or duty match
Edge selection
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