Explanation Of Registers - Fujitsu FR60 Hardware Manual

19.2

Explanation of Registers

This section describes the registers used by the data internal RAM/instruction internal
RAM access restriction functions.
■ DRLR: Data RAM Limit Control Register (D-Bus RAM Limit Control Register)
The configuration of the data RAM limit control register is shown below:
Address : 00000390
Initial value
[Bits 7 to 2] Reserved bits
These bits are reserved bits. If writing data to these bits, be sure to write "0". The values read from these
bits are undefined.
[Bits 1, 0] DL1 and DL0
These bits limit the RAM area available for the stack.
DL1
0
0
1
1
Note:
Do not set a value that exceeds the RAM capacity installed on the device. If the setting is rewritten,
insert at least one NOP instruction immediately after that processing.
7 6 5
- - -
H
- - -
DL0
0 (Setting not allowed)
1 The 4K bytes area at addresses 40000
value).
0 The 8K bytes area at addresses 40000
1 The 16K bytes area at addresses 40000
4 3 2 1
- - - DL1
- - - 0
Explanation
to 40FFF
H
to 41FFF
H
H
0
DL0 (R/W)
1
can be used (initial
H
can be used.
H
to 43FFF can be used.
H
577