Input Capture Operation - Fujitsu FR60 Hardware Manual

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
14.3.3

Input Capture Operation

In 16-bit input capture operation, an interrupt can be generated upon detection of at the
specified valid edge, fetching the 16-bit free-run timer value and writing it to the capture
register.
■ 16-bit Input Capture Operation
Figure 14.3-2 shows the timing for data fetching by the input capture module.
Counter value
FFFF
BFFF
7FFF
3FFF
0000
Reset
IN 0
IN 1
IN 2
Data register 0
Data register 1
Data register 2
Capture 0 interrupt
Capture 1 interrupt
Capture 2 interrupt
Capture 0: Rising edge
Capture 1: Falling edge
Capture 2: Both edges
■ Input Timing for 16-bit Input Capture
Figure 14.3-3 shows the timing of signal input for a 16-bit input capture operation.
430
Figure 14.3-2 Sample of Input Capture Fetch Timing
H
H
H
H
H
Undefined 3FFF
H
Undefined
Undefined
Figure 14.3-3 Input Timing for 16-bit Input Capture
φ
Counter value
Input capture input
Capture signal
Capture register
Interrupt
BFFF
H
BFFF 7FFF
H H
Generating an interrupt again at a valid edge
Clearing the interrupt by software
N N+1
Valid edge
Time
N+1