Internal Architecture - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.2.1

Internal Architecture

This section describes the features and structure of the internal architecture.
■ Features of the Internal Architecture
• RISC architecture used
Basic instruction: One instruction per cycle
• 32-bit architecture
General-purpose register: 32 bits x 16
• 4 GB linear memory space
• Multiplier installed
32-bit by 32-bit multiplication: 5 cycles
16-bit by 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed: 6 cycles
Support of multiple interrupts
Level mask function: 16 levels
• Enhanced instructions for I/O operations
Memory-to-memory transfer instruction
Bit-processing instructions
• Efficient code
Basic instruction word length: 16 bits
• Low-power consumption
Sleep and stop modes
Gear function
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