Fujitsu FR60 Hardware Manual page 272

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CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers

[Bit 6] CTUT: Counter write bit

This bit transfers data from RCR to UDCR.

When this bit is set to "1", data is transferred from RCR to UDCR.

Writing "0" to this bit has no effect. The read value is always "0".

Do not set this bit to "1" during counting (when the CSTR bit of the CSR is "1").

[Bit 5] UCRE: UDCR clear enable bit

This bit controls the compare operation that clears UDCR.

UDCR clear functions other than clearing due to comparing (such as due to the ZIN pin) are not

[Bit 4] RLDE: Reload enable bit

This bit controls the start of the reload function. When the reload function is started, if UDCR leads the

underflow, this bit transfers the value of RCR to UDCR.

[Bit 3] UDCC: UDCR clear bit

This bit clears the UDCR. When this bit is set to "0", the UDCR is cleared to 0000

Writing "1" to this bit has no effect. The read value is always "1".

[Bit 2] CGSC: Counter clear/gate selection bit

This bit selects the function of the external pin ZIN.

Disables counter clear (initial value).

Enables counter clear.

Disables the reload function (initial value).

Enables the reload function.

Counter clear function (initial value)

Gate function

Counter clear by compare

Reload function

ZIN function

Mb91350a series