Fujitsu FR60 Hardware Manual page 235

■ CS → RD/WR Setup (TYP[3:0] =0101
Figure 4.6-3 shows setting of the CS → RD/WR setup.
READ
WRITE
Setting "1" for the CS → RD/WR setup delay (AWR1) enables the multiplex address output cycle to be
•
extended by one cycle as shown in Figure 4.6-3 , allowing the address to be latched directly to the rising
edge of AS. Use this setting if you want to use AS as an ALE (Address Latch Enable) strobe without
using MCLK.
, AWR=100B
B
Figure 4.6-3 Setting of CS → RD/WR Setup
MCLK
A[23:0]
AS
CSn
RD
D[31:16]
WR
D[31:16]
)
H
address[23:0]
address[15:0] data[15:0]
data[15:0]
address[15:0]
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