Fujitsu FR60 Hardware Manual page 456

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
■ Timing of 16-bit Output Compare Operation
The output level can be changed using two pairs of compare registers (when CMOD = 1).
In output compare operation, a compare match signal is generated when the free-running timer value
matches the specified compare register value. The output value can be reversed and an interrupt can be
issued. The output reverse timing upon a compare match is synchronized with the counter count timing.
[Compare register write timing]
If the value of a compare register is changed, the value is not compared with the counter value.
Figure 14.4-4 shows the timing for writing data to a compare register.
Compare clear register 0 value
Compare clear register 1 value
[Compare match and interrupt timing]
Figure 14.4-5 shows the timing for compare match and the interrupt.
Compare register value
[Pin output timing]
Figure 14.4-6 shows the timing for pin output.
Compare register value
438
Figure 14.4-4 Compare Register Write Timing
Counter value
Compare register 0 write
Compare register 1 write
Figure 14.4-5 Timing of Compare Match and Interrupt
φ
Count clock
Counter value
Compare match
Pin output
Interrupt
Figure 14.4-6 Pin Output Timing
Counter value
Compare match
Pin output
N N+1
No match signal is generated.
M N+1
L
Compare 0
stop
N N+1
N
N N+1
N
N+2 N+3
N+3
Compare 1
stop
N+3
N+2
N N+1