Fujitsu FR60 Hardware Manual page 244

CHAPTER 4 EXTERNAL BUS INTERFACE
■ 2-Cycle Transfer (External → I/O) (TYP[3:0] = 0000
Figure 4.8-4 shows setting of 2-cycle transfer (external → I/O).
When a wait has not been set on the memory and the I/O side
FR30
compatible mode
Basic mode
• The bus is accessed in the same way as an interface when the DMAC transfer is not performed.
• In basic mode, DACKn/EOPn is outputted in both transfer source bus access and transfer destination
bus access.
226
Figure 4.8-4 Setting of 2-Cycle Transfer (External → I/O)
MCLK
memory address
A[23:0]
AS
CSn
RD
CSn
WRn
D[31:16]
DACKn
EOPn
DACKn
EOPn
DREQn
, AWR = 0008 , and IOWR = 00
B H
idle I/O address
)
H