Fujitsu FR60 Hardware Manual page 414

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
[Bit 5] FRE (FRaming Error)
This bit, which is an interrupt request flag, is set when a framing error occurs during reception.
To clear the flag when it has been set, write "0" to the REC bit of the SCR register.
If the FRE bit is set, the SIDR data becomes invalid.
Value
Notes:
• Switch the internal and external baud rate clocks using Bit 3 of the serial mode register only while
the UART is stopped, since the switching takes effect immediately after writing.
• Bit 3 of the serial mode register is write-only.
[Bit 4] RDRF (Receiver Data Register Full)
This bit, which is an interrupt request flag, indicates that the SIDR register has receive data.
This bit is set when receive data is loaded into the SIDR register. It is automatically cleared when the
data is read from the SIDR register.
Value
[Bit 3] TDRE (Transmitter Data Register Empty)
This bit, which is an interrupt request flag, indicates whether send data can be written to SODR.
This bit is cleared when send data is written to the SODR register. It is set again when the written data
is loaded into the send shifter and begins to be transferred, indicating that the next send data can be
written.
Value
396
0 No framing error has occurred. [initial value]
1 A framing error has occurred.
0 No receive data exists. [initial value]
1 Receive data exists.
0 Disables writing of send data.
1 Enables writing of send data. [initial value]
Meaning
Meaning
Meaning