Fujitsu FR60 Hardware Manual page 409

[Bit 3] CS0 (Clock Select)
This bit selects the UART operating clock.
Value
0
1
[Bit 2, 1] (reserved)
Always write "0" to these bits.
[Bit 0] (reserved)
This bit is unused.
■ Serial Control Register (SCR)
The bit configuration of the serial control register (SCR) is shown below.
Note: The MB91F353A/351A/352A/353A do not have SCR ch4.
SCR
Address : ch0 000062
ch1 00006A
ch2 000072
ch3 0000C2
ch3 0000CA
The SCR controls the transfer protocol that is used for serial communication.
[Bit 7] PEN (Parity Enable)
This bit specifies whether to add parity in serial communication when data communication is
performed.
Value
0
1
Note:
Parity can be added only in normal mode (Mode 0) of asynchronous (start-stop synchronization)
communication mode. No parity can be added in multiprocessor mode (Mode 1) and CLK
synchronous communication mode (Mode 2).
Built-in timer (U-TIMER) [initial value]
External clock
7 6 5
H
H
PEN P SBL
H R/W R/W R/W
H
H
No parity [initial value]
Parity
Meaning
4 3 2
CL A/D REC RXE
R/W R/W W R/W
Meaning
1 0 Initial value
00000100
TXE
R/W
B
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