Fujitsu FR60 Hardware Manual page 191

[Bits 3 to 0] TYP[3:0] (TYPe select)
These bits set the access type of each chip select area as indicated in the following table:
TYP3 TYP2
0
1
0
x
0
0
0
1
1
1
1
1
Set the access type as the combination of all bits.
*
: CS area mask setting function
If you want to set an area some of whose operation settings are changed for a certain CS area (referred to as
the base setting area), you can set TYPE3 to "0" of ACR in another CS area to "1111" so that the area can
function as a mask setting area.
If you do not use the mask setting function, disable any overlapping area settings for multiple CS areas.
Access operations to the mask setting area are as follows:
• CSX corresponding to a mask setting area is not asserted.
• CSX corresponding to a base setting area is not asserted.
• For the following ACR settings, the settings on the mask setting area side are valid:
• Bits [11:10]DBW[1:0]: Bus width setting
• Bits [9:8]BST[1:0]: Burst length setting
• Bit [7]SREN: Sharing-enable setting
• Bit [6]PFEN: Prefetch-enable setting
TYP1 TYP0
Normal access (asynchronous SRAM, I/O, and
x x
single/page)
Address data multiplex access (8/16-bit bus width
x x
only)
x 0 Disable WAIT insertion by the RDY pin.
Enable WAIT insertion by the RDY pin (disabled
x 1
during bursts).
Use the WR0 to WR3 pins as write strobes (WR is
0 x
always H).
1 x Setting disabled
0 Setting disabled
0
1 Setting disabled
1 0 Setting disabled
1 1 Setting disabled
0 0 Setting disabled
0 1 Setting disabled
1 0 Setting disabled
Mask area setting (The access type is the same as
1 1
that of the overlapping area)
Access type
*
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