Fujitsu FR60 Hardware Manual page 472

2
CHAPTER 15 I C INTERFACE
A sample flow is given below.
7. Example of occurrence of an interrupt (INT bit=1) upon detection of "AL bit=1"
When an instruction which generates a start condition is executed (setting the MSS bit to "1") with
"bus busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection
of "AL bit=1".
Figure 15.2-3 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
454
Master mode setting
Set the MSS bit in the bus control register (IBCR) to "1".
Wait* for the time for three-bit data transmission at the I
transfer frequency set in the clock control register (ICCR).
BB bit=0 and AL bit=1?
YES
Set the EN bit to "0" to initialize I
Start Condition
SLAVE ADDRESS
2
C
NO
to normal process
2
C.
Interrupt in the ninth clock cycle
ACK DAT
Clearing the AL bit by software
Releasing the SCL by clearing
the INT bit by software