Fujitsu FR60 Hardware Manual page 642

INDEX
CLKT
External Bus Clock (CLKT) .............................. 109
Clock Control Register
Clock Control Register (ICCR).......................... 455
Clock Controller
Clock Controller................................................. 34
Clock Disable Register
Clock Disable Register (IDBL).......................... 463
Clock Generation
Block Diagram of Clock Generation Controller
.......................................................... 111
Clock Mode
Note on Operating in PLL Clock Mode ................ 33
Clock Operation
Clock Operation ............................................... 292
Clock Source Control Register
Clock Source Control Register (CLKR).............. 120
Clock Supply
Operation of Clock Supply Function .......... 147, 153
Command Sequence
Automatic Algorithm Command Sequence ......... 548
Communication Error
Communication Error that Causes No Error ........ 467
Compare
Reload and Compare Functions ......................... 261
Up/Down Counting with an Arbitrary Width
when the Reload and Compare Functions are
Started................................................ 262
Compare Register
Compare Register (OCCP0 to OCCP7) .............. 434
Comparison
Comparison of Functions ...................................... 6
Condition Code Register
CCR (Condition Code Register)........................... 58
Configuration
Configuration of Area Configuration Registers 0 to 7
(ACR0 to ACR7) ................................ 169
Configuration of ASR0 to ASR3
(Area Select Registers) ........................ 168
Configuration of AWR0 to AWR3
(Area Wait Registers) .......................... 175
Configuration of General Control Register 10
.......................................................... 310
Configuration of General Control Register 20
.......................................................... 313
Configuration of Interrupt Control Register (ICR)
............................................................ 75
Configuration of PPG Cycle Setting Register
(PCSR)............................................... 307
Configuration of PPG Duty Setting Register
(PDUT) .............................................. 308
Configuration of PPG Timer Register (PTMR)
.......................................................... 309
624
Configuration of the Chip Select Enable Register
(CSER) .............................................. 183
Configuration of the Flash Control/Status Register
(FLCR) (CPU Mode) .......................... 540
Configuration of the Flash Memory Wait Register
(FLWC) ............................................. 543
Configuration of the I/O Wait Registers for DMAC
(IOWR0 to IOWR3)............................ 181
Configuration of the Terminal and Timing Control
Register (TCR) ................................... 184
Configurations of Control Status Registers ......... 303
Connection
Connection Between the MB91350A Device and the
Endian Areas ...................................... 200
Continuing Transfer
Timing of the DREQ Pin Input for Continuing
Transfer Over the Same Channel .......... 520
Control Register
Setting of Temporary Stopping by Writing to the
Control Register (Set Independently for Each
Channel or all Channels
Simultaneously) .................................. 511
Control Signal
Control Signals on the Ordinary Bus Interface
......................................................... 189
Control Signals on the Time Division I/O
Interface............................................. 189
Control Status Register
Bit Configuration of the Control Status Register
(ADCS1)............................................ 367
Bit Configuration of the Control Status Register
(ADCS2)............................................ 370
Configurations of Control Status Registers ......... 303
Control Status Register (TMCSR) ..................... 289
Conversion Time Setting Register
Bit Configuration of the Conversion Time Setting
Register (ADCT) ................................ 373
Coprocessor Error Trap
Coprocessor Error Trap ...................................... 89
Correspondence
Correspondence between the Memory Space Area and
Peripheral Resource Registers .............. 583
Counter
Block Diagram of the 8/16-bit Up/Down
Counters/Timers (ch0)......................... 250
Characteristics of the 8/16-bit Up/Down
Counters/Timers ................................. 247
Clearing of the Counter for the 16-bit Free-running
Timer................................................. 284
Counter Control Register High/Low ch0
(CCR H/L ch0) ................................... 252
Counter Control Register High/Low ch1
(CCR H/L ch1) ................................... 256
Counter Status Register 0/1 (CSR0/1) ................ 256