Fujitsu FR60 Hardware Manual page 518

CHAPTER 16 DMA CONTROLLER (DMAC)
■ Step Transfer
If "1" is set as the block size, a step transfer sequence is generated.
[Features of a step transfer]
• If a transfer request is received, the transfer request is cleared after one transfer operation and then the
transfer is stopped (The DMA transfer request to the bus controller is canceled).
• Another request occurring during transfer is ignored.
• If a transfer request for another channel with a higher priority is received during transfer, the channel is
switched after the transfer is stopped and then restarted. Priority in a step transfer is valid only if
transfer requests occur simultaneously.
■ Block Transfer
If any value other than "1" is specified as the block size, a block transfer sequence is generated.
[Features of a block transfer]
• The block transfer has the same features as those of a step transfer except that one transfer unit consists
of multiple transfer cycle counts (number of blocks). Figure 16.3-3 shows an example of block transfer.
Transfer request (
Bus operation
Number of blocks
Transfer count
Transfer end
(Example of block transfer where block transfer is started by rising-edge detection at an external
pin, the number of blocks is "2", and the transfer count is "2".)
■ Step/Block Transfer 2-Cycle Transfer Fly-by Transfer
This transfer has the same features as those of a 2-cycle transfer except that the transfer area can only be
external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only.
Table 16.3-6 lists the specifiable transfer addresses for step/block transfer 2-cycle transfer fly-by transfer.
Table 16.3-6 Specifiable Transfer Addresses for Step/Block Transfer 2-Cycle Transfer Fly-
Transfer source addressing
Specification not required (invalid)
500
Figure 16.3-3 Example of Block Transfer
edge)
CPU SA DA
21
2
by Transfer
SA DA CPU SA
0
Direction Transfer destination addressing
None
DA SA DA
2 1
1
External area