Fujitsu FR60 Hardware Manual page 118

CHAPTER 3 CPU AND CONTROL UNITS
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Returning from an abnormal state when PLL is selected
If, while the device is operating with PLL as the source clock, an abnormal condition
control, the device automatically enters an oscillation stabilization wait time to assure the PLL lock time.
When the oscillation stabilization wait time has elapsed, the device enters the normal operating state.
*: The multiply-by rate is changed while PLL is working, or an incorrect bit such as a bit equivalent to PLL
operation enable bit is generated.
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Occurrence of a watchdog reset when main clock oscillation has been stopped by the subclock
If, while the subclock is operating as the source clock, a watchdog reset occurs when main clock oscillation
has been stopped due to bit 0 (OSCDS1 bit) of the OSCCR (oscillation control register), the device enters
an oscillation stabilization wait immediately after the reset (INIT) is cleared.
When the oscillation stabilization wait time elapses, the device enters the operation initialization reset
(RST) state.
There is no wait for oscillation stabilization when the OSCDS1 bit is "0" for the subclock or when the main
clock is the source clock.
■ Selecting an Oscillation Stabilization Wait Time
The oscillation stabilization wait time is measured with the built-in timebase counter.
If a source for an oscillation stabilization wait occurs and the device enters the oscillation stabilization wait
state, the built-in timebase counter is initialized and then it starts to measure the oscillation stabilization
wait time.
Using Bits 3 and 2 (OS1 and OS0 bits) of the standby control register (STCR), select and set one of the
four types for oscillation stabilization wait time.
Once selected, a setting is initialized only if a settings initialization reset (INIT) is generated due to the
external INIT pin. The oscillation stabilization wait time that has been set before a reset is maintained if a
settings initialization reset (INIT) is generated or an operation initialization reset (RST) is generated due to
a watchdog reset condition.
The four types of oscillation stabilization wait time settings are designed for the following four types of
use:
• OS1, OS0=00: No oscillation stabilization wait time
(if neither PLL nor the oscillator should stop in stop mode)
• OS1, OS0=01: PLL lock wait time
(if an oscillator should not stop in stop mode)
• OS1, OS0=10: Oscillation stabilization wait time (intermediate)
(if an oscillator that stabilizes quickly, such as a ceramic vibrator, is used)
• OS1, OS0=11: Oscillation stabilization wait time (long)
(if an ordinary quartz oscillator will be used)
100
*
occurs in PLL