Fujitsu FR60 Hardware Manual page 234

CHAPTER 4 EXTERNAL BUS INTERFACE
As with the normal interface, auto-wait (AWR[15:12]), read → write idle cycle (AWR[7:6]), write
•
recovery (AWR[5:4]), address → CS delay (AWR[2]), CS → RD/WR setup delay (AWR[1]), and RD/
WR → CS hold delay (AWR[0]) can be set.
• In areas for which the address/data multiplex interface is set, set "1" (DBW[1:0]=00
length.
■ With External Wait (TYP[3:0]=0101
Figure 4.6-2 shows setting of the address/data multiplex interface with an external wait.
Figure 4.6-2 Setting of Address/Data Multiplex Interface With an External Wait
READ
WRITE
• Making a setting such as TYP[3:0]=01x1
multiplex interface.
216
, AWR=1008
B
MCLK
A[23:0]
AS
CSn
RD
D[31:16]
address[15:0]
WR
address[15:0]
D[31:16]
RDY
)
H
address[23:0]
data[15:0]
data[15:0]
Release
External wait
in the ACR register enables RDY input in the address/data
B
) as the burst
B