Operation Of The 16-Bit Free-Running Timer - Fujitsu FR60 Hardware Manual

CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER
7.1.3

Operation of the 16-bit Free-Running Timer

The 16-bit free-running timer starts counting from counter value 0000 after a reset.
This counter value is used as the reference time for 16-bit output compare and 16-bit
input capture operation.
■ Clearing of the Counter for the 16-bit Free-running Timer
The counter is cleared when any of the following conditions occurs:
• An overflow occurs.
• The value of the counter compare matches the value of the compare clear register (the compare register
for output compare ch0). (A mode setting is required).
• A 1 is written to the CLR bit of the TCCS register during timer operation.
• 0000
• A reset is performed.
An interrupt can be generated when an overflow occurs or when the values of the counter correspond to the
compare clear register 0. (A mode setting is required for the compare match interrupt.)
Figure 7.1-2 shows how the counter is cleared for an overflow. Figure 7.1-3 shows how the counter is
cleared on a compare match of the values for the counter and the compare clear register.
Figure 7.1-3 Clearing of Counter on Compare Match with Value of the Compare Clear Register
Compare register
284
is written to the TCDT register while the timer is stopped.
H
Figure 7.1-2 Clearing of Counter for Overflow
Counter value
Reset
Interrupt
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
BFFF
Interrupt
Match
H
Time
Match
Time