Fujitsu FR60 Hardware Manual page 311

■ Underflow Operation
An underflow is an event in which the counter value changes from 0000
occurs at the count of [Reload register setting value + 1].
If the RELD bit of the control register is set to "1" when an underflow occurs, the contents of the reload
register are loaded into the counter and the count operation is continued. If the RELD bit is set to "0", the
counter stops at FFFF
An underflow sets the UF bit of the control register and, if the INTE bit is set to "1", generates an interrupt
request.
Figure 7.2-3 shows the timing chart for the underflow operation.
Count clock
Counter
Data load
Underflow set
Count clock
Counter
Underflow set
.
H
Figure 7.2-3 Timing Chart for the Underflow Operation
0000 H
[RELD=1]
0000 H
[RELD=0]
Reload data -1
FFFF H
to FFFF . Thus, an underflow
H H
-1 -1
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