Control Status Registers (Adcs0 And Adcs1) - Fujitsu F2MC-16LX Hardware Manual
Mb90550a/b series, 16-bit
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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CHAPTER 15 A/D CONVERTER
15.2.1 Control Status Registers (ADCS0 and ADCS1)
The control status registers (ADCS0 and ADCS1) control the A/D converter and
represent its status.
■ Control Status Registers (ADCS0 and ADCS1)
Do not rewrite data to ADCS0 during A/D conversion.
Figure 15.2-2 Control Status Registers (ADCS0 and ADCS1)
Higher byte of the
control status register
Address:00003D
Read/write
Initial value
Lower byte of the
control status register
Address:00003C
Read/write
Initial value
Note:
Please do not rewrite ADCS1 while the A/D conversion is operating.
[bit15] BUSY (Busy flag and stop)
The BUSY bit is used to represent the operating status of the A/D converter.
❍ At read:
This bit is set at activation of the A/D converter and cleared at termination. That is, the A/D
converter pauses when this bit is 0 and operates when the bit is "1".
❍ At write:
If 0 is written to this bit during A/D operation, the A/D conversion is forced to be stopped during
successive and pause mode.
You cannot write 1 to the busy bit. In the read modify write (RMW) system instruction, "1" is
read. In single mode, the bit is cleared upon A/D conversion completion. In successive and stop
modes, the bit is not cleared until the converter is terminated by writing "0".
Note:
Do not perform a forced termination and activation at the same time with software. (BUSY =
0, STRT = 1)
[bit14] INT (Interrupt)
INT is used to display data and is set when the conversion data is written to ADCR.
If this bit is set when the INTE bit is "1", an interrupt request is generated. If the EI
activation is allowed, the EI
This setting is cleared by writing "0" in this bit or with an EI
"1" is read in read modify write (RMW) system instruction.
236
bit
15
14
13
BUSY INT
INTE
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
bit
7
6
MD1
MD0
ANS2 ANS1 ANS0 ANE2
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
2
OS is activated. Writing "1" is meaningless.
12
11
10
PAUS STS1
STS0 STRT
(0)
(0)
(0)
5
4
3
2
(0)
(0)
(0)
2
9
8
ADCS1
Reserved
(W)
(-)
(0)
(0)
1
0
ANE1 ANE0
ADCS0
(0)
(0)
OS interrupt clear signal.
2
OS
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