Fujitsu FR60 Hardware Manual page 135

■ Timebase Counter Control Register (TBCR)
The configuration of the timebase counter control register is shown below:
The timebase counter control register controls timebase timer interrupts, among other things.
This register enables timebase timer interrupts, selects an interrupt interval time, and sets an optional
function for the reset operation.
[Bit 15] TBIF (TimeBasetimer Interrupt Flag)
This bit is the timebase timer interrupt flag.
It indicates that the interval time (TBC2-0 bits, which are Bits 13-11) specified by the timebase counter
has elapsed.
A timebase timer interrupt request is generated if this bit is set to "1" when interrupts are enabled by Bit
14 (TBIE bit, TBIE=1).
Clear source
Set source
• This bit is initialized to "0" by a reset (RST).
• This bit is readable and writable, although only "0" can be written to it. Writing "1" does not change the
bit value.
The value read by a read modify write instruction is always "1".
[Bit 14] TBIE (TimeBasetimer Interrupt Enable)
This bit is the timebase timer interrupt request output enable bit.
It controls output of an interrupt request when the interval time of the timebase counter has elapsed. A
time-base timer interrupt request is generated if bit 15 (TBIF bit) is set to "1" when this bit is set to "1".
Value
• This bit is initialized to "0" by a reset (RST).
• This bit is readable and writable.
bit
Address: 00000482
H
Initial value (INIT)
Initial value (RST)
An instruction writes "0".
The specified interval time elapses (the trailing edge of the timebase counter is
detected).
0 timebase timer interrupt request output disabled (initial value)
1 timebase timer interrupt request output enabled
15 14 13
TBIF TBIE TBC2 TBC1
R/W R/W R/W R/W
0 0 X
0 0 X
Explanation
12 11 10
TBC0 - SYNCR SYNCS
R/W R/W R/W
X X X
X X X
9 8
R/W
0 0
X X
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