Fujitsu FR60 Hardware Manual page 274

CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers
■ Counter Control Register High/Low ch1 (CCR H/L ch1)
The bit configuration of the counter control register high/low (ch1) (CCRH/L ch1) is shown below.
Address : 0000B8
0000B9
[Bit 15] (reserved)
This bit is reserved. This bit must always be set to "0".
[Bits 14 to 0]
For details of these bits, see the explanation for CCRH/L ch0.
■ Counter Status Register 0/1 (CSR0/1)
The bit configuration of the counter status register 0/1 (CSR0/1) is shown below.
Address : 0000B7
0000BB
[Bit 7] CSTR: Count start bit
This bit controls the start and stop of UDCR counting.
CSTR
0
1
[Bit 6] CITE: Compare interrupt output control bit
This bit controls whether to enable or disable interrupt output to the CPU when a compare detection
flag (CMPF) is set (during a compare operation).
CITE
0
1
256
bit 15 14 13
Reserved CDCF CFIE
H
R/W R/W R/W
H
7 6 5
Reserved CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W R/W R/W
bit 7 6 5
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
H
R/W R/W R/W
H
Stops the counting operation (initial value)
Starts the counting operation
Disables compare interrupt output (initial value).
Enables compare interrupt output.
12 11 10
CLKS CMS1 CMS0 CES1
R/W R/W R/W R/W
4 3 2
R/W R/W R/W R/W
4 3 2
R/W R/W R/W
Operation
Compare interrupt output
9 8 Initial value
CES0 00000000
B
R/W
1 0 Initial value
00001000
B
R/W
1 0 Initial value
00000000
B
R R