Fujitsu FR60 Hardware Manual page 484

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CHAPTER 15 I C INTERFACE
■ Master Addressing
In master mode, BB = 1 and TRX = 1 are set after a START condition is generated and the IDAR register
contents are outputted starting with the MSB. After address data is sent and an acknowledge is received
from a slave device, bit 0 of the send data (bit 0 of the IDAR register after transmission) is inverted and
stored in the TRX bit. This operation is also performed for a repeated START condition.
Two bytes are sent for a 10-bit slave address during write access. The first byte consists of the header
section (11110, A9, A8, 0) that indicates a 10-bit sequence, and the second byte consists of the low-order 8
bits of the slave address (A7 to A0).
The 10-bit slave device in the read access state sends the above bytes and generates a repeated START
condition as well as the header section (11110, A9, A8, 1) that indicates a read access.
7-bit slave
address
10-bit slave
access
■ Arbitration
Arbitration occurs if other master devices are also sending data during sending in master mode. If data sent
by the local device is 1 and the data on the SDA line is the "L" level, the local device assumes arbitration to
have been lost and sets AL=1.
AL = 1 is set if the interface detects an unnecessary START condition in the first bit of the data or neither a
START condition nor a STOP condition can be generated.
If arbitration loss is detected, MSS = 0 and TRX = 0 are set and the device enters slave receive mode and
returns an acknowledge when it receives the device's own slave address.
■ Acknowledge
The receiving device sends an acknowledge to the sending device. The ACK bit (IBCR) can specify
whether an acknowledge is sent when data is received.
Even if an acknowledge is not returned from the master during data transmission in slave mode (read
access from other master devices), the TRX bit is set to "0" and the device enters receive mode. This allows
the master to generate a STOP condition when the slave releases the SCL line.
In master mode, an acknowledge from the slave can be checked by reading the LRB bit (IBSR).
■ Bus Error
A bus error is recognized and the I
• A violation of the basic convention on the I
detected.
• A stop condition in master mode is detected.
• A violation of the basic convention on the I
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Write START condition - A6 A5 A4 A3 A2 A1 A0 0
Read START condition - A6 A5 A4 A3 A2 A1 A0 1
Write START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0
Read START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0
Repeated START condition - 1 1 1 1 0 A9 A8 1
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C interface is stopped if:
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C bus during data transfer (including the Ack bit) is
2
C bus while the bus is idle is detected.