Hold Request Cancellation Request Register (Hrcl) - Fujitsu FR60 Hardware Manual

9.2.2

Hold request cancellation request register (HRCL)

The hold request cancellation request register (HRCL) is used to set an interrupt level
for generating a hold request cancellation request.
■ Bit Configuration of the Hold Request Cancellation Request Register (HRCL)
The bit configuration of the hold request cancellation request register (HRCL) is shown below.
Address :00000045
[Bit 7] MHALTI
This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request sets this bit to
"1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit the same way it would
be cleared in a normal interrupt routine.
[Bits 4 to 0] LVL4 to 0
These bits set the interrupt level used to issue a hold request cancellation request to the bus master.
If an interrupt request with a higher level than the level defined in the HRCL register occurs, a hold
request cancellation request is issued to the bus master.
The LVL4 bit is always "1"; "0" cannot be written to this bit.
bit 7 6 5
MHALTI - -
H
R/W
4 3 2
LVL4 LVL3 LVL2 LVL1
R R/W R/W R/W
1 0 HRCL
LVL0
0--11111
R/W
(Initial value)
331