Fujitsu FR60 Hardware Manual page 659

SRCL
DMAC Interrupt Source Clear Register (SRCL)
.......................................................... 418
SRST
Software Reset (STCR: SRST Bit Writing) .......... 97
SSP
SSP (System Stack Pointer) ................................ 62
System Stack Pointer (SSP) ................................ 77
SSR
Serial Status Register (SSR).............................. 395
Stack
Interrupt Stack ................................................... 78
Mapping of the Stack to the Little-endian Area
............................................................ 40
Standby
Return from Standby ........................................ 348
Standby Control Register
Standby Control Register (STCR)...................... 114
Standby Mode
Return from Standby Mode (Sleep/Stop) ............ 338
Standby Operation
Normal and Synchronous Standby Operations
.......................................................... 142
Start
Shift Operation Start/Stop Timing and I/O
Timing ............................................... 421
START Condition............................................ 464
Starting
Starting from a Temporary Stop ........................ 508
Starting External Access
Basic Conditions for Starting External Access Using
Prefetch
.......................................................... 218
Starting Transfer
Starting Transfer .............................................. 508
Start-stop Synchronization
Asynchronous (Start-stop Synchronization)
Mode ................................................. 400
State
Device Operating States.................................... 135
Device States................................................... 134
Explanation of Terms Used in the Pin State
Lists................................................... 597
Overview of Device State Control ..................... 133
Pin States in Each CPU State ............................ 598
States of Serial I/O Interface Operation .............. 420
Status
Automatic Algorithm Execution Status .............. 546
Bit Configuration of the Control Status Register
(ADCS1)............................................ 367
Bit Configuration of the Control Status Register
(ADCS2)............................................ 370
Bus Status Register (IBSR) ............................... 445
Configuration of the Flash Control/Status Register
(FLCR) (CPU Mode) ...........................540
Configurations of Control Status Registers..........303
Control Status Register (TMCSR) ......................289
Counter Status Register 0/1 (CSR0/1).................256
PS (Program Status)............................................57
Serial Mode Control Status Register (SMCS)
..........................................................413
Serial Status Register (SSR) ..............................395
Timer Control Status Register (TCCS)................281
STCR
Software Reset (STCR: SRST Bit Writing) ...........97
Standby Control Register (STCR) ......................114
Step
Step/Block Transfer 2-Cycle Transfer Fly-by
Transfer ..............................................500
Step Trace Trap
Operation of Step Trace Trap...............................88
Step Transfer
Step Transfer....................................................500
Step/Block Transfer
Step/Block Transfer 2-Cycle Transfer.................499
Stop
Return from Standby Mode (Sleep/Stop).............338
Shift Operation Start/Stop Timing and I/O
Timing................................................421
Starting from a Temporary Stop .........................508
STOP Condition ...............................................464
Transfer Stop Requests from Peripheral
Circuits...............................................513
Stop Mode
Stop Mode .......................................................140
Wait Time after Returning from Stop Mode ........107
Stopping
Setting of Temporary Stopping by Writing to the
Control Register (Set Independently for Each
Channel or all Channels
Simultaneously)...................................511
Store
Load and Store ...................................................53
Structure
Structure Assignment ..........................................39
Structure of the Internal Architecture....................51
Subclock
Note for the Case of Using No Subclock ...............33
Wait Time after Switching From the Subclock to the
Main Clock .........................................107
Subclock Switching
Subclock Switching ............................................34
Successive Access
Basic Timing (For Successive Accesses)
(TYP[3:0]=0000
INDEX
) ..........205
,AWR=0008
B H
641