Fujitsu FR60 Hardware Manual page 10

3.9.2 Reset Sources ............................................................................................................................. 96
3.9.3 Reset Sequence .......................................................................................................................... 98
3.9.4 Oscillation Stabilization Wait Time .............................................................................................. 99
3.9.5 Reset Operation Modes ............................................................................................................. 102
3.10 Clock Generation Control ............................................................................................................... 104
3.10.1 PLL Controls .............................................................................................................................. 105
3.10.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time .................................................... 106
3.10.3 Clock Distribution ....................................................................................................................... 108
3.10.4 Clock Division ............................................................................................................................ 110
3.10.5 Block Diagram of Clock Generation Controller .......................................................................... 111
3.10.6 Register of Clock Generation Controller .................................................................................... 112
3.10.7 Peripheral Circuits of Clock Controller ....................................................................................... 129
3.11 Device State Control ....................................................................................................................... 133
3.11.1 Device States and State Transitions ......................................................................................... 134
3.11.2 Low-power Consumption Modes ............................................................................................... 138
3.12 Watch Timer ................................................................................................................................... 143
3.13 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 149
3.14 Peripheral Stop Control .................................................................................................................. 155
CHAPTER 4 EXTERNAL BUS INTERFACE ................................................................ 161
4.1 Overview of the External Bus Interface .......................................................................................... 162
4.2 External Bus Interface Registers .................................................................................................... 167
4.2.1 ASR0 to ASR3 (Area Select Register) ...................................................................................... 168
4.2.2 ACR0 to ACR7 (Area Configuration Registers) ......................................................................... 169
4.2.3 AWR0 to AWR3 (Area Wait Register) ....................................................................................... 175
4.2.4 IOWR0 to IOWR3 (I/O Wait Registers for DMAC) ..................................................................... 181
4.2.5 Chip Select Enable Register (CSER) ........................................................................................ 183
4.2.6 TCR (Terminal and Timing Control Register) ............................................................................ 184
4.3 Setting Example of the Chip Select Area ........................................................................................ 186
4.4 Byte Ordering (Endian) and Bus Access ........................................................................................ 188
4.4.1 Relationship Between Data Bus Widths and Control Signals .................................................... 189
4.4.2 Big Endian Bus Access ............................................................................................................. 190
4.4.3 Little Endian Bus Access ........................................................................................................... 197
4.4.4 External Access ......................................................................................................................... 201
4.5 Ordinary Bus Interface .................................................................................................................... 205
4.6 Address/data Multiplex Interface .................................................................................................... 215
4.7 Prefetch Operation .......................................................................................................................... 218
4.8 DMA Access Operation .................................................................................................................. 222
4.9 Bus Arbitration ................................................................................................................................ 228
4.10 Procedure for Setting a Register .................................................................................................... 230
CHAPTER 5 I/O PORT .................................................................................................. 231
5.1 Overview of the I/O Port ................................................................................................................. 232
5.2 I/O Port Registers ........................................................................................................................... 234
CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers ................................. 245
6.1 8/16-bit Up/Down Counters/Timers ................................................................................................ 246
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