Fujitsu FR60 Hardware Manual page 228

CHAPTER 4 EXTERNAL BUS INTERFACE
■ Synchronous Write Enable Output Timing (TYP[3:0]=0000
Figure 4.5-6 shows the synchronous write enable output timing.
Read
Write
• If synchronous write enable output is enabled (If the W03 bit of the AWR is "1"), operation is as
follows.
• WR0 to WR1 pin output asserts synchronous write enable output at the timing at which AS pin output is
asserted. For a write to an external bus, the synchronous write enable output is L. For a read from an
external bus, the synchronous write enable output is "H".
• Write data is outputted from the external data output pin at the clock cycle at which synchronous write
enable output is asserted.
• Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of WR0 to
WR3 and WR output timing. Use it as it is for controlling the data I/O. If synchronous write enable
output is used, the following restrictions apply:
Do not set the following additional wait because the timing for synchronous write enable output
becomes meaningless:
- CS → RD/WR setup (Always write "0" to the W01 bit of AWR)
- First wait cycle setting (Always write "0000" to bits W15 of W12 of AWR)
Do not set the following access types (TYPE3 to TYPE0 bits (Bit 3 to Bit 0) in the ACR register) because
the timing for synchronous write enable output becomes meaningless:
- Multiplex bus setting (Always write "0" to the TYPE2 bit of ACR)
- RDY input enable setting (Always write "0" to the TYPE0 bit of ACR)
For synchronous write enable output, always set the burst length to "1" (set bits BST1 and BST0 to
"0").
210
Figure 4.5-6 Synchronous Write Enable Output Timing
MCLK
A[23:0]
AS
CSn
RD
D[31:16]
WRn
D[31:16]
,AWR=0000
B
#1 #2
#1
#2
#1 #2
)
H