Input Capture Module Registers - Fujitsu FR60 Hardware Manual

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
14.3.2

Input Capture Module Registers

This section describes the configuration and functions of the registers used by the
input capture operation.
The input capture module has the following two types of registers:
• Input capture data register (IPCP0 to IPCP3)
• Input capture control register (ICS01 and ICS23)
■ Input Capture Data Register (IPCP0 to IPCP3)
The bit configuration of the input capture data register (IPCP0 to IPCP3) is shown below.
IPCP0 to 3
Address : 0000DA
H
0000D8
H
0000DE
H
0000DC
H
The input capture data register is used to store the value of the 16-bit free-running timer on detection of a
valid edge of the waveform input via the corresponding external input pin. When this register is reset, its
value is undefined.
This register must be accessed in 16-bit or 32-bit units. This register cannot be written.
■ Input Capture Control Registers (ICS01 and ICS23)
The bit configurations of the input capture control registers (ICS01 and ICS23) are shown below.
ICS23
Address : 0000E1
H
ICS01
Address : 0000E3
H
428
15 14 13
CP15 CP14 CP13 CP12
R R R
7 6 5
CP07 CP06 CP05 CP04
R R R
15 14 13
ICP3 ICP2 ICE3 ICE2
R/W R/W R/W R/W
7 6 5
ICP1 ICP1 ICE1 ICE0
R/W R/W R/W R/W
12 11 10 9
CP11 CP10 CP09
R R R R
4 3 2 1
CP03 CP02 CP01
R R R R
12 11 10 9
EG31 EG30 EG21
R/W R/W R/W
4 3 2 1
EG11 EG10 EG01
R/W R/W R/W
8 Initial value:
XXXXXXXX
CP08
B
R
0 Initial value:
XXXXXXXX
CP00
B
R
8 Initial value:
00000000
EG20
B
R/W
0 Initial value:
00000000
EG00
B
R/W