Fujitsu FR60 Hardware Manual page 610

APPENDIX
Table A-1 I/O Map (10 / 10)
Address
+0
000B70
H
to
000BFC
H
000C00
H
000C04
H
to
000C14
H
000C18
H
to
000FFC
H
001000
H
001004
H
001008
H
00100C
H
001010
H
001014
H
001018
H
00101C
H
001020
H
001024
H
001028
H
to
001FFC
H
FLCR[R/W]
007000
H
0110X000
FLWC[R/W]
007004
H
00010011
________
007008
H
________
00700C
H
________
007010
H
007014
H
to
0070FF
H
592
Register
+1
________
Test register (access is not allowed.)
Test register (access is not allowed.)
________
DMASA0[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA0[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA1[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA1[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA2[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA2[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA3[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA3[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA4[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA4[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
________
________
________
________
________
________
________
+2
________ ________
________ ________
________ ________
________ ________
________ ________
Block
+3
Reserved
Interrupt control
unit
R-bus test
Reserved
DMAC
DMAC
Reserved
Flash memory
Reserved