Memory Map - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.5

Memory Map

This section describes the memory maps of the FR family microcontrollers.
■ Memory Map
The address space is 32 bits linear.
Figure 3.5-1 shows the memory map.
●
Direct addressing area
The following areas in the address space are the areas for I/O. When direct addressing is used in these
areas, an operand address can be directly specified in an instruction.
The size of an address area for which an address can be directly specified varies is determined by the data
length as follows:
• Byte data (8 bits): 000
• Halfword data (16 bits): 000
• Word data (32 bits): 000
●
Vector table initial area
The area from 000FFC00
You can place the vector table that will be used during EIT processing at any address by rewriting the TBR.
Initialization by a reset places the table at this address.
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Figure 3.5-1 Memory Map
0000 0000
H
Byte data
0000 0100
H
Halfword data
0000 0200
H
Word data
0000 0400
H
000F FC00
H
Vector table
initial area
000F FFFF
H
FFFF FFFF
H
to 0FF
H H
to 1FF
H
to 3FF
H
to 000FFFFF
H
Direct addressing area
H
H
is the initial EIT vector table area.
H