Fujitsu FR60 Hardware Manual page 241

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When successive accesses are made within the same chip select area without negating the chip select,

neither CS → RD/WR setup delay nor RD/WR → CS hold delay is inserted.

If a setup cycle for determining the address or a hold cycle for determining the address is needed, set

"1" for the address → CS delay setting (W02 bit of the AWR register).

For I/O on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O

hold wait cycle is generated.

For memory on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is

generated. The I/O hold wait cycle does not affect the write strobe.

However, the address and CS signal are retained until the fly-by bus access cycles end.

■ DMA Fly-By Transfer (Memory → I/O) (TYP[3:0]=0000

Figure 4.8-2 shows setting of DMA fly-by transfer (memory → I/O).

When a wait has not been set on the memory side

Figure 4.8-2 Setting of DMA Fly-by Transfer (Memory → I/O)

memory address

, and IOWR=41

Sense timing in

Mb91350a series